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LM3S6965 Microcontroller

Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C

This register provides a summary of the interrupt status of the individual PWM generator blocks. A bit set to 1 indicates that the corresponding generator block is asserting an interrupt. The individual interrupt status registers in each block must be consulted to determine the reason for the interrupt, andusedtocleartheinterrupt. Forthefaultinterrupt,awriteof1tothatbitpositionclearsthelatched interrupt status.

PWM Interrupt Status and Clear (PWMISC)

Base 0x4002.8000

Offset 0x01C

Type R/W1C, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

IntFault

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W1C

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

IntPWM2

IntPWM1

IntPWM0

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:17

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

16

IntFault

R/W1C

0

Fault Interrupt Asserted

 

 

 

 

Indicates that the fault input is asserting an interrupt.

15:3

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

2

IntPWM2

RO

0

PWM2 Interrupt Status

 

 

 

 

Indicates if the PWM generator 2 block is asserting an interrupt.

1

IntPWM1

RO

0

PWM1 Interrupt Status

 

 

 

 

Indicates if the PWM generator 1 block is asserting an interrupt.

0

IntPWM0

RO

0

PWM0 Interrupt Status

 

 

 

 

Indicates if the PWM generator 0 block is asserting an interrupt.

November 16, 2008

501

Preliminary

Pulse Width Modulator (PWM)

Register 9: PWM Status (PWMSTATUS), offset 0x020

This register provides the status of the FAULT input signal.

PWM Status (PWMSTATUS)

Base 0x4002.8000

Offset 0x020

Type RO, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Fault

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:1

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

0

Fault

RO

0

Fault Interrupt Status

 

 

 

 

When set, indicates the fault input is asserted.

502

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 10: PWM0 Control (PWM0CTL), offset 0x040

Register 11: PWM1 Control (PWM1CTL), offset 0x080

Register 12: PWM2 Control (PWM2CTL), offset 0x0C0

TheseregistersconfigurethePWMsignalgenerationblocks(PWM0CTLcontrolsthePWMgenerator 0 block, and so on). The Register Update mode, Debug mode, Counting mode, and Block Enable mode are all controlled via these registers. The blocks produce the PWM signals, which can be either two independent PWM signals (from the same counter), or a paired set of PWM signals with dead-band delays added.

The PWM0 block produces the PWM0 and PWM1 outputs, the PWM1 block produces the PWM2 and PWM3 outputs, and the PWM2 block produces the PWM4 and PWM5 outputs.

PWM0 Control (PWM0CTL)

Base 0x4002.8000

Offset 0x040

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

reserved

 

 

 

 

CmpBUpd CmpAUpd LoadUpd

Debug

Mode

Enable

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:6

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

5

CmpBUpd

R/W

0

Comparator B Update Mode

 

 

 

 

Same as CmpAUpd but for the comparator B register.

4

CmpAUpd

R/W

0

Comparator A Update Mode

 

 

 

 

The Update mode for the comparator A register. When not set, updates

 

 

 

 

to the register are reflected to the comparator the next time the counter

 

 

 

 

is 0. When set, updates to the register are delayed until the next time

 

 

 

 

thecounteris0afterasynchronousupdatehasbeenrequestedthrough

 

 

 

 

the PWM Master Control (PWMCTL) register (see page 494).

3

LoadUpd

R/W

0

Load Register Update Mode

 

 

 

 

The Update mode for the load register. When not set, updates to the

 

 

 

 

registerarereflectedtothecounterthenexttimethecounteris0. When

 

 

 

 

set, updates to the register are delayed until the next time the counter

 

 

 

 

is 0 after a synchronous update has been requested through the PWM

 

 

 

 

Master Control (PWMCTL) register.

2

Debug

R/W

0

Debug Mode

 

 

 

 

The behavior of the counter in Debug mode. When not set, the counter

 

 

 

 

stopsrunningwhenitnextreaches0,andcontinuesrunningagainwhen

 

 

 

 

no longer in Debug mode. When set, the counter always runs.

November 16, 2008

503

Preliminary

Pulse Width Modulator (PWM)

Bit/Field

Name

Type

Reset

Description

1

Mode

R/W

0

Counter Mode

 

 

 

 

The mode for the counter. When not set, the counter counts down from

 

 

 

 

the load value to 0 and then wraps back to the load value (Count-Down

 

 

 

 

mode). When set, the counter counts up from 0 to the load value, back

 

 

 

 

down to 0, and then repeats (Count-Up/Down mode).

0

Enable

R/W

0

PWM Block Enable

 

 

 

 

Master enable for the PWM generation block. When not set, the entire

 

 

 

 

block is disabled and not clocked. When set, the block is enabled and

 

 

 

 

produces PWM signals.

504

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 13: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 Register 14: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 Register 15: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4

TheseregisterscontroltheinterruptandADCtriggergenerationcapabilitiesofthePWMgenerators (PWM0INTEN controls the PWM generator 0 block, and so on). The events that can cause an interrupt or an ADC trigger are:

The counter being equal to the load register

The counter being equal to zero

The counter being equal to the comparator A register while counting up

The counter being equal to the comparator A register while counting down

The counter being equal to the comparator B register while counting up

The counter being equal to the comparator B register while counting down

Any combination of these events can generate either an interrupt, or an ADC trigger; though no determination can be made as to the actual event that caused an ADC trigger if more than one is specified.

PWM0 Interrupt and Trigger Enable (PWM0INTEN)

Base 0x4002.8000

Offset 0x044

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

reserved

TrCmpBD TrCmpBU TrCmpAD TrCmpAU

TrCntLoad

TrCntZero

reserved

IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad

IntCntZero

Type

RO

RO

R/W

R/W

R/W

R/W

R/W

R/W

RO

RO

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:14

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

13

TrCmpBD

R/W

0

Trigger for Counter=Comparator B Down

 

 

 

 

When 1, a trigger pulse is output when the counter matches the

 

 

 

 

comparator B value and the counter is counting down.

12

TrCmpBU

R/W

0

Trigger for Counter=Comparator B Up

 

 

 

 

When 1, a trigger pulse is output when the counter matches the

 

 

 

 

comparator B value and the counter is counting up.

11

TrCmpAD

R/W

0

Trigger for Counter=Comparator A Down

 

 

 

 

When 1, a trigger pulse is output when the counter matches the

 

 

 

 

comparator A value and the counter is counting down.

November 16, 2008

505

Preliminary

Pulse Width Modulator (PWM)

Bit/Field

Name

Type

Reset

Description

10

TrCmpAU

R/W

0

Trigger for Counter=Comparator A Up

 

 

 

 

When 1, a trigger pulse is output when the counter matches the

 

 

 

 

comparator A value and the counter is counting up.

9

TrCntLoad

R/W

0

Trigger for Counter=Load

 

 

 

 

When 1, a trigger pulse is output when the counter matches the

 

 

 

 

PWMnLOAD register.

8

TrCntZero

R/W

0

Trigger for Counter=0

 

 

 

 

When 1, a trigger pulse is output when the counter is 0.

7:6

reserved

RO

0x0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

5

IntCmpBD

R/W

0

Interrupt for Counter=Comparator B Down

 

 

 

 

When1,aninterruptoccurswhenthecountermatchesthecomparatorB

 

 

 

 

value and the counter is counting down.

4

IntCmpBU

R/W

0

Interrupt for Counter=Comparator B Up

 

 

 

 

When1,aninterruptoccurswhenthecountermatchesthecomparatorB

 

 

 

 

value and the counter is counting up.

3

IntCmpAD

R/W

0

Interrupt for Counter=Comparator A Down

 

 

 

 

When1,aninterruptoccurswhenthecountermatchesthecomparatorA

 

 

 

 

value and the counter is counting down.

2

IntCmpAU

R/W

0

Interrupt for Counter=Comparator A Up

 

 

 

 

When1,aninterruptoccurswhenthecountermatchesthecomparatorA

 

 

 

 

value and the counter is counting up.

1

IntCntLoad

R/W

0

Interrupt for Counter=Load

 

 

 

 

When1,aninterruptoccurswhenthecountermatchesthePWMnLOAD

 

 

 

 

register.

0

IntCntZero

R/W

0

Interrupt for Counter=0

 

 

 

 

When 1, an interrupt occurs when the counter is 0.

506

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 16: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 Register 17: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 Register 18: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8

These registers provide the current set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller (PWM0RIS controls the PWM generator 0 block, and so on). Bits set to 1 indicate the latched events that have occurred; bits set to 0 indicate that the event in question has not occurred.

PWM0 Raw Interrupt Status (PWM0RIS)

Base 0x4002.8000

Offset 0x048

Type RO, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

reserved

 

 

 

 

IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad

IntCntZero

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:6

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

5

IntCmpBD

RO

0

Comparator B Down Interrupt Status

 

 

 

 

Indicates that the counter has matched the comparator B value while

 

 

 

 

counting down.

4

IntCmpBU

RO

0

Comparator B Up Interrupt Status

 

 

 

 

Indicates that the counter has matched the comparator B value while

 

 

 

 

counting up.

3

IntCmpAD

RO

0

Comparator A Down Interrupt Status

 

 

 

 

Indicates that the counter has matched the comparator A value while

 

 

 

 

counting down.

2

IntCmpAU

RO

0

Comparator A Up Interrupt Status

 

 

 

 

Indicates that the counter has matched the comparator A value while

 

 

 

 

counting up.

1

IntCntLoad

RO

0

Counter=Load Interrupt Status

 

 

 

 

Indicates that the counter has matched the PWMnLOAD register.

0

IntCntZero

RO

0

Counter=0 Interrupt Status

 

 

 

 

Indicates that the counter has matched 0.

November 16, 2008

507

Preliminary

Pulse Width Modulator (PWM)

Register 19: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C Register 20: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C Register 21: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC

These registers provide the current set of interrupt sources that are asserted to the controller (PWM0ISC controlsthePWMgenerator0block,andsoon). Bitssetto1indicatethelatchedevents that have occurred; bits set to 0 indicate that the event in question has not occurred. These are R/W1C registers; writing a 1 to a bit position clears the corresponding interrupt reason.

PWM0 Interrupt Status and Clear (PWM0ISC)

Base 0x4002.8000

Offset 0x04C

Type R/W1C, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

reserved

 

 

 

 

IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad

IntCntZero

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W1C

R/W1C

R/W1C

R/W1C

R/W1C

R/W1C

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:6

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

5

IntCmpBD

R/W1C

0

Comparator B Down Interrupt

 

 

 

 

Indicates that the counter has matched the comparator B value while

 

 

 

 

counting down.

4

IntCmpBU

R/W1C

0

Comparator B Up Interrupt

 

 

 

 

Indicates that the counter has matched the comparator B value while

 

 

 

 

counting up.

3

IntCmpAD

R/W1C

0

Comparator A Down Interrupt

 

 

 

 

Indicates that the counter has matched the comparator A value while

 

 

 

 

counting down.

2

IntCmpAU

R/W1C

0

Comparator A Up Interrupt

 

 

 

 

Indicates that the counter has matched the comparator A value while

 

 

 

 

counting up.

1

IntCntLoad

R/W1C

0

Counter=Load Interrupt

 

 

 

 

Indicates that the counter has matched the PWMnLOAD register.

0

IntCntZero

R/W1C

0

Counter=0 Interrupt

 

 

 

 

Indicates that the counter has matched 0.

508

November 16, 2008

Preliminary

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