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LM3S6965 Microcontroller

Offset

Name

Type

Reset

Description

See

page

 

 

 

 

 

0x0C0

PWM2CTL

R/W

0x0000.0000

PWM2 Control

503

0x0C4

PWM2INTEN

R/W

0x0000.0000

PWM2 Interrupt and Trigger Enable

505

0x0C8

PWM2RIS

RO

0x0000.0000

PWM2 Raw Interrupt Status

507

0x0CC

PWM2ISC

R/W1C

0x0000.0000

PWM2 Interrupt Status and Clear

508

0x0D0

PWM2LOAD

R/W

0x0000.0000

PWM2 Load

509

0x0D4

PWM2COUNT

RO

0x0000.0000

PWM2 Counter

510

0x0D8

PWM2CMPA

R/W

0x0000.0000

PWM2 Compare A

511

0x0DC

PWM2CMPB

R/W

0x0000.0000

PWM2 Compare B

512

0x0E0

PWM2GENA

R/W

0x0000.0000

PWM2 Generator A Control

513

0x0E4

PWM2GENB

R/W

0x0000.0000

PWM2 Generator B Control

516

0x0E8

PWM2DBCTL

R/W

0x0000.0000

PWM2 Dead-Band Control

519

0x0EC

PWM2DBRISE

R/W

0x0000.0000

PWM2 Dead-Band Rising-Edge Delay

520

0x0F0

PWM2DBFALL

R/W

0x0000.0000

PWM2 Dead-Band Falling-Edge-Delay

521

18.5Register Descriptions

The remainder of this section lists and describes the PWM registers, in numerical order by address offset.

November 16, 2008

493

Preliminary

Pulse Width Modulator (PWM)

Register 1: PWM Master Control (PWMCTL), offset 0x000

This register provides master control over the PWM generation blocks.

PWM Master Control (PWMCTL)

Base 0x4002.8000

Offset 0x000

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

GlobalSync2 GlobalSync1 GlobalSync0

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:3

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

2

GlobalSync2

R/W

0

Update PWM Generator 2

 

 

 

 

Same as GlobalSync0 but for PWM generator 2.

1

GlobalSync1

R/W

0

Update PWM Generator 1

 

 

 

 

Same as GlobalSync0 but for PWM generator 1.

0

GlobalSync0

R/W

0

Update PWM Generator 0

 

 

 

 

Setting this bit causes any queued update to a load or comparator

 

 

 

 

register in PWM generator 0 to be applied the next time the

 

 

 

 

correspondingcounterbecomeszero. Thisbitautomaticallyclearswhen

 

 

 

 

the updates have completed; it cannot be cleared by software.

494

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004

This register provides a method to perform synchronization of the counters in the PWM generation blocks. Writing a bit in this register to 1 causes the specified counter to reset back to 0; writing multiplebitsresetsmultiplecounterssimultaneously. Thebitsauto-clearaftertheresethasoccurred; reading them back as zero indicates that the synchronization has completed.

PWM Time Base Sync (PWMSYNC)

Base 0x4002.8000

Offset 0x004

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

Sync2

Sync1

Sync0

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:3

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

2

Sync2

R/W

0

Reset Generator 2 Counter

 

 

 

 

Performs a reset of the PWM generator 2 counter.

1

Sync1

R/W

0

Reset Generator 1 Counter

 

 

 

 

Performs a reset of the PWM generator 1 counter.

0

Sync0

R/W

0

Reset Generator 0 Counter

 

 

 

 

Performs a reset of the PWM generator 0 counter.

November 16, 2008

495

Preliminary

Pulse Width Modulator (PWM)

Register 3: PWM Output Enable (PWMENABLE), offset 0x008

This register provides a master control of which generated PWM signals are output to device pins. BydisablingaPWMoutput,thegenerationprocesscancontinue(forexample,whenthetimebases are synchronized) without driving PWM signals to the pins. When bits in this register are set, the corresponding PWM signal is passed through to the output stage, which is controlled by the PWMINVERT register. When bits are not set, the PWM signal is replaced by a zero value which is also passed to the output stage.

PWM Output Enable (PWMENABLE)

Base 0x4002.8000

Offset 0x008

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

reserved

 

 

 

 

PWM5En PWM4En PWM3En PWM2En PWM1En PWM0En

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:6

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

5

PWM5En

R/W

0

PWM5 Output Enable

 

 

 

 

When set, allows the generated PWM5 signal to be passed to the device

 

 

 

 

pin.

4

PWM4En

R/W

0

PWM4 Output Enable

 

 

 

 

When set, allows the generated PWM4 signal to be passed to the device

 

 

 

 

pin.

3

PWM3En

R/W

0

PWM3 Output Enable

 

 

 

 

When set, allows the generated PWM3 signal to be passed to the device

 

 

 

 

pin.

2

PWM2En

R/W

0

PWM2 Output Enable

 

 

 

 

When set, allows the generated PWM2 signal to be passed to the device

 

 

 

 

pin.

1

PWM1En

R/W

0

PWM1 Output Enable

 

 

 

 

When set, allows the generated PWM1 signal to be passed to the device

 

 

 

 

pin.

0

PWM0En

R/W

0

PWM0 Output Enable

 

 

 

 

When set, allows the generated PWM0 signal to be passed to the device

 

 

 

 

pin.

496

November 16, 2008

Preliminary

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