Pulse Width Modulator (PWM)

18.2.6Synchronization Methods

There is a global reset capability that can synchronously reset any or all of the counters in the PWM generators. If multiple PWM generators are configured with the same counter load value, this can be used to guarantee that they also have the same count value (this does imply that the PWM generatorsmustbeconfiguredbeforetheyaresynchronized). Withthis,morethantwoPWMsignals can be produced with a known relationship between the edges of those signals since the counters always have the same values.

The counter load values and comparator match values of the PWM generator can be updated in two ways. The first is immediate update mode, where a new value is used as soon as the counter reaches zero. By waiting for the counter to reach zero, a guaranteed behavior is defined, and overly short or overly long output PWM pulses are prevented.

Theotherupdatemethodissynchronous,wherethenewvalueisnotuseduntilaglobalsynchronized update signal is asserted, at which point the new value is used as soon as the counter reaches zero. This second mode allows multiple items in multiple PWM generators to be updated simultaneously without odd effects during the update; everything runs from the old values until a pointatwhichtheyallrunfromthenewvalues. TheUpdatemodeoftheloadandcomparatormatch values can be individually configured in each PWM generator block. It typically makes sense to use thesynchronousupdatemechanismacrossPWMgeneratorblockswhenthetimersinthoseblocks are synchronized, though this is not required in order for this mechanism to function properly.

18.2.7Fault Conditions

There are two external conditions that affect the PWM block; the signal input on the Fault pin and the stalling of the controller by a debugger. There are two mechanisms available to handle such conditions: the output signals can be forced into an inactive state and/or the PWM timers can be stopped.

Each output signal has a fault bit. If set, a fault input signal causes the corresponding output signal to go into the inactive state. If the inactive state is a safe condition for the signal to be in for an extended period of time, this keeps the output signal from driving the outside world in a dangerous manner during the fault condition. A fault condition can also generate a controller interrupt.

Each PWM generator can also be configured to stop counting during a stall condition. The user can select for the counters to run until they reach zero then stop, or to continue counting and reloading. A stall condition does not generate a controller interrupt.

18.2.8Output Control Block

With each PWM generator block producing two raw PWM signals, the output control block takes care of the final conditioning of the PWM signals before they go to the pins. Via a single register, the set of PWM signals that are actually enabled to the pins can be modified; this can be used, for example, to perform commutation of a brushless DC motor with a single register write (and without modifyingtheindividualPWMgenerators,whicharemodifiedbythefeedbackcontrolloop). Similarly, fault control can disable any of the PWM signals as well. A final inversion can be applied to any of the PWM signals, making them active Low instead of the default active High.

18.3Initialization and Configuration

The following example shows how to initialize the PWM Generator 0 with a 25-KHz frequency, and witha25%dutycycleonthe PWM0 pinanda75%dutycycleonthe PWM1 pin. Thisexampleassumes the system clock is 20 MHz.

Preliminary

LM3S6965 Microcontroller

1.Enable the PWM clock by writing a value of 0x0010.0000 to the RCGC0 register in the System Control module.

2.EnabletheclocktotheappropriateGPIOmoduleviathe RCGC2 registerintheSystemControl module.

3.In the GPIO module, enable the appropriate pins for their alternate function using the

GPIOAFSEL register.

4.Configure the Run-Mode Clock Configuration (RCC) register in the System Control module to use the PWM divide (USEPWMDIV) and set the divider (PWMDIV) to divide by 2 (000).

5.Configure the PWM generator for countdown mode with immediate updates to the parameters.

■Write the PWM0CTL register with a value of 0x0000.0000.

■Write the PWM0GENA register with a value of 0x0000.008C.

■Write the PWM0GENB register with a value of 0x0000.080C.

6.Set the period. For a 25-KHz frequency, the period = 1/25,000, or 40 microseconds. The PWM clock source is 10 MHz; the system clock divided by 2. This translates to 400 clock ticks per period. Use this value to set the PWM0LOAD register. In Count-Down mode, set the Load field in the PWM0LOAD register to the requested period minus one.

■Write the PWM0LOAD register with a value of 0x0000.018F.

7.Set the pulse width of the PWM0 pin for a 25% duty cycle.

■Write the PWM0CMPA register with a value of 0x0000.012B.

8.Set the pulse width of the PWM1 pin for a 75% duty cycle.

■Write the PWM0CMPB register with a value of 0x0000.0063.

9.Start the timers in PWM generator 0.

■Write the PWM0CTL register with a value of 0x0000.0001.

10.Enable PWM outputs.

■Write the PWMENABLE register with a value of 0x0000.0003.

18.4Register Map

Table 18-1 on page 491 lists the PWM registers. The offset listed is a hexadecimal increment to the register’s address, relative to the PWM base address of 0x4002.8000.

Table 18-1. PWM Register Map

Preliminary

Pulse Width Modulator (PWM)

Preliminary