LM3S6965 Microcontroller

2.2.2Embedded Trace Macrocell (ETM)

ETM was not implemented in the Stellaris® devices. This means Chapters 15 and 16 of the ARM® Cortex™-M3 Technical Reference Manual can be ignored.

2.2.3Trace Port Interface Unit (TPIU)

The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace Port Analyzer. The Stellaris® devices have implemented TPIU as shown in Figure 2-2 on page 45. This is similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference Manual, however, SWJ-DP only provides SWV output for the TPIU.

Figure 2-2. TPIU Block Diagram

2.2.4ROM Table

The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical Reference Manual.

2.2.5Memory Protection Unit (MPU)

TheMemoryProtectionUnit(MPU)isincludedontheLM3S6965controllerandsupportsthestandard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system.

2.2.6Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC):

■Facilitates low-latency exception and interrupt handling

■Controls power management

■Implements system control registers

Preliminary