LM3S6965 Microcontroller

Figure 18-2. PWM Module Block Diagram

PWM Generator Block

18.2Functional Description

18.2.1PWM Timer

The timer in each PWM generator runs in one of two modes: Count-Down mode or Count-Up/Down mode. In Count-Down mode, the timer counts from the load value to zero, goes back to the load value, and continues counting down. In Count-Up/Down mode, the timer counts from zero up to the load value, back down to zero, back up to the load value, and so on. Generally, Count-Down mode is used for generating leftor right-aligned PWM signals, while the Count-Up/Down mode is used for generating center-aligned PWM signals.

The timers output three signals that are used in the PWM generation process: the direction signal (this is always Low in Count-Down mode, but alternates between Low and High in Count-Up/Down mode),asingle-clock-cycle-widthHighpulsewhenthecounteriszero,andasingle-clock-cycle-width High pulse when the counter is equal to the load value. Note that in Count-Down mode, the zero pulse is immediately followed by the load pulse.

18.2.2PWM Comparators

There are two comparators in each PWM generator that monitor the value of the counter; when eithermatchthecounter,theyoutputasingle-clock-cycle-widthHighpulse. WheninCount-Up/Down mode,thesecomparatorsmatchbothwhencountingupandwhencountingdown;theyaretherefore qualified by the counter direction signal. These qualified pulses are used in the PWM generation process. Ifeithercomparatormatchvalueisgreaterthanthecounterloadvalue,thenthatcomparator never outputs a High pulse.

Figure 18-3 on page 488 shows the behavior of the counter and the relationship of these pulses whenthecounterisinCount-Downmode.Figure18-4onpage488showsthebehaviorofthecounter and the relationship of these pulses when the counter is in Count-Up/Down mode.

Preliminary

Pulse Width Modulator (PWM)

Figure 18-3. PWM Count-Down Mode

Load

Zero

A

B

Dir

BDown

ADown

Figure 18-4. PWM Count-Up/Down Mode

Load

CompA

CompB

Zero

Load

Zero

A

B

Dir

18.2.3PWM Signal Generator

The PWM generator takes these pulses (qualified by the direction signal), and generates two PWM signals. In Count-Down mode, there are four events that can affect the PWM signal: zero, load, match A down, and match B down. In Count-Up/Down mode, there are six events that can affect the PWM signal: zero, load, match A down, match A up, match B down, and match B up. The match A or match B events are ignored when they coincide with the zero or load events. If the match A and match B events coincide, the first signal, PWMA, is generated based only on the match A event, and the second signal, PWMB, is generated based only on the match B event.

Foreachevent,theeffectoneachoutputPWMsignalisprogrammable:itcanbeleftalone(ignoring the event), it can be toggled, it can be driven Low, or it can be driven High. These actions can be used to generate a pair of PWM signals of various positions and duty cycles, which do or do not overlap. Figure 18-5 on page 489 shows the use of Count-Up/Down mode to generate a pair of center-aligned, overlapped PWM signals that have different duty cycles.

Preliminary

LM3S6965 Microcontroller

Figure 18-5. PWM Generation Example In Count-Up/Down Mode

Load

CompA

CompB

Zero

PWMA

PWMB

In this example, the first generator is set to drive High on match A up, drive Low on match A down, and ignore the other four events. The second generator is set to drive High on match B up, drive Low on match B down, and ignore the other four events. Changing the value of comparator A changes the duty cycle of the PWMA signal, and changing the value of comparator B changes the duty cycle of the PWMB signal.

18.2.4Dead-Band Generator

The two PWM signals produced by the PWM generator are passed to the dead-band generator. If disabled, the PWM signals simply pass through unmodified. If enabled, the second PWM signal is lostandtwoPWMsignalsaregeneratedbasedonthefirstPWMsignal. ThefirstoutputPWMsignal is the input signal with the rising edge delayed by a programmable amount. The second output PWMsignalistheinversionoftheinputsignalwithaprogrammabledelayaddedbetweenthefalling edge of the input signal and the rising edge of this new signal.

This is therefore a pair of active High signals where one is always High, except for a programmable amount of time at transitions where both are Low. These signals are therefore suitable for driving a half-H bridge, with the dead-band delays preventing shoot-through current from damaging the powerelectronics. Figure18-6onpage489showstheeffectofthedead-bandgeneratoronaninput PWM signal.

Figure 18-6. PWM Dead-Band Generator

18.2.5Interrupt/ADC-Trigger Selector

The PWM generator also takes the same four (or six) counter events and uses them to generate an interrupt or an ADC trigger. Any of these events or a set of these events can be selected as a sourceforaninterrupt;whenanyoftheselectedeventsoccur,aninterruptisgenerated. Additionally, thesameevent,adifferentevent,thesamesetofevents,oradifferentsetofeventscanbeselected as a source for an ADC trigger; when any of these selected events occur, an ADC trigger pulse is generated. The selection of events allows the interrupt or ADC trigger to occur at a specific position within the PWM signal. Note that interrupts and ADC triggers are based on the raw events; delays in the PWM signal edges caused by the dead-band generator are not taken into account.

Preliminary