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LM3S6965 Microcontroller

Table 17-2. Analog Comparators Register Map

Offset

Name

Type

Reset

Description

See

page

 

 

 

 

 

0x000

ACMIS

R/W1C

0x0000.0000

Analog Comparator Masked Interrupt Status

478

0x004

ACRIS

RO

0x0000.0000

Analog Comparator Raw Interrupt Status

479

0x008

ACINTEN

R/W

0x0000.0000

Analog Comparator Interrupt Enable

480

0x010

ACREFCTL

R/W

0x0000.0000

Analog Comparator Reference Voltage Control

481

0x020

ACSTAT0

RO

0x0000.0000

Analog Comparator Status 0

482

0x024

ACCTL0

R/W

0x0000.0000

Analog Comparator Control 0

483

0x040

ACSTAT1

RO

0x0000.0000

Analog Comparator Status 1

482

0x044

ACCTL1

R/W

0x0000.0000

Analog Comparator Control 1

483

17.5Register Descriptions

The remainder of this section lists and describes the Analog Comparator registers, in numerical order by address offset.

November 16, 2008

477

Preliminary

Analog Comparators

Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000

This register provides a summary of the interrupt status (masked) of the comparators.

Analog Comparator Masked Interrupt Status (ACMIS)

Base 0x4003.C000

Offset 0x000

Type R/W1C, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

IN1

IN0

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W1C

R/W1C

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:2

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

1

IN1

R/W1C

0

Comparator 1 Masked Interrupt Status

 

 

 

 

Gives the masked interrupt state of this interrupt. Write 1 to this bit to

 

 

 

 

clear the pending interrupt.

0

IN0

R/W1C

0

Comparator 0 Masked Interrupt Status

 

 

 

 

Gives the masked interrupt state of this interrupt. Write 1 to this bit to

 

 

 

 

clear the pending interrupt.

478

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004

This register provides a summary of the interrupt status (raw) of the comparators.

Analog Comparator Raw Interrupt Status (ACRIS)

Base 0x4003.C000

Offset 0x004

Type RO, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

IN1

IN0

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:2

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

1

IN1

RO

0

Comparator 1 Interrupt Status

 

 

 

 

Whenset,indicatesthataninterrupthasbeengeneratedbycomparator

 

 

 

 

1.

0

IN0

RO

0

Comparator 0 Interrupt Status

 

 

 

 

Whenset,indicatesthataninterrupthasbeengeneratedbycomparator

 

 

 

 

0.

November 16, 2008

479

Preliminary

Analog Comparators

Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008

This register provides the interrupt enable for the comparators.

Analog Comparator Interrupt Enable (ACINTEN)

Base 0x4003.C000

Offset 0x008

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

IN1

IN0

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:2

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

1

IN1

R/W

0

Comparator 1 Interrupt Enable

 

 

 

 

Whenset,enablesthecontrollerinterruptfromthecomparator1output.

0

IN0

R/W

0

Comparator 0 Interrupt Enable

 

 

 

 

Whenset,enablesthecontrollerinterruptfromthecomparator0output.

480

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register4:AnalogComparatorReferenceVoltageControl(ACREFCTL),offset

0x010

This register specifies whether the resistor ladder is powered on as well as the range and tap.

Analog Comparator Reference Voltage Control (ACREFCTL)

Base 0x4003.C000

Offset 0x010

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

reserved

 

 

EN

RNG

 

reserved

 

 

 

VREF

 

Type

RO

RO

RO

RO

RO

RO

R/W

R/W

RO

RO

RO

RO

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:10

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

9

EN

R/W

0

Resistor Ladder Enable

 

 

 

 

The EN bit specifies whether the resistor ladder is powered on. If 0, the

 

 

 

 

resistor ladder is unpowered. If 1, the resistor ladder is connected to

 

 

 

 

the analog VDD.

 

 

 

 

This bit is reset to 0 so that the internal reference consumes the least

 

 

 

 

amount of power if not used and programmed.

8

RNG

R/W

0

Resistor Ladder Range

 

 

 

 

The RNG bit specifies the range of the resistor ladder. If 0, the resistor

 

 

 

 

ladder has a total resistance of 31 R. If 1, the resistor ladder has a total

 

 

 

 

resistance of 23 R.

7:4

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

3:0

VREF

R/W

0x00

Resistor Ladder Voltage Ref

 

 

 

 

The VREF bitfieldspecifiestheresistorladdertapthatispassedthrough

an analog multiplexer. The voltage corresponding to the tap position is the internal reference voltage available for comparison. See Table 17-1 on page 475 for some output reference voltage examples.

November 16, 2008

481

Preliminary

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