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LM3S6965 Microcontroller

Register 26: Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17

Thisregisterenablessoftwaretoselectthesourcethatcausesthe LED1 and LED0 signalstotoggle.

Ethernet PHY Management Register 23 – LED Configuration (MR23)

Base 0x4004.8000

Address 0x17

Type R/W, reset 0x0010

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

reserved

 

 

 

 

LED1[3:0]

 

 

LED0[3:0]

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

Bit/Field

Name

Type

Reset

Description

15:8

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

7:4

LED1[3:0]

R/W

0x1

LED1 Source

 

 

 

 

The LED1 field selects the source that toggles the LED1 signal.

 

 

 

 

Value Description

0x0 Link OK

0x1 RX or TX Activity (Default LED1)

0x2 Reserved

0x3 Reserved

0x4 Reserved

0x5 100BASE-TX mode

0x6 10BASE-T mode

0x7 Full-Duplex

0x8 Link OK & Blink=RX or TX Activity

3:0

LED0[3:0]

R/W

0x0

LED0 Source

The LED0 field selects the source that toggles the LED0 signal.

Value Description

0x0 Link OK (Default LED0)

0x1 RX or TX Activity

0x2 Reserved

0x3 Reserved

0x4 Reserved

0x5 100BASE-TX mode

0x6 10BASE-T mode

0x7 Full-Duplex

0x8 Link OK & Blink=RX or TX Activity

November 16, 2008

471

Preliminary

Ethernet Controller

Register27:EthernetPHYManagementRegister24 –MDI/MDIXControl(MR24), address 0x18

This register enables software to control the behavior of the MDI/MDIX mux and its switching capabilities.

Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24)

Base 0x4004.8000

Address 0x18

Type R/W, reset 0x00C0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

reserved

 

 

 

PD_MODEAUTO_SW MDIX MDIX_CM

 

MDIX_SD

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

RO

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

15:8

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

7

PD_MODE

R/W

0

Parallel Detection Mode

 

 

 

 

Whenset,enablestheParallelDetectionmodeandallowsauto-switching

 

 

 

 

to work when auto-negotiation is not enabled.

6

AUTO_SW

R/W

0

Auto-Switching Enable

 

 

 

 

When set, enables Auto-Switching of the MDI/MDIX mux.

5

MDIX

R/W

0

Auto-Switching Configuration

 

 

 

 

When set, indicates that the MDI/MDIX mux is in the crossover (MDIX)

 

 

 

 

configuration.

 

 

 

 

When 0, it indicates that the mux is in the pass-through (MDI)

 

 

 

 

configuration.

 

 

 

 

When the AUTO_SW bit is 1, the MDIX bit is read-only. When the

 

 

 

 

AUTO_SW bit is 0, the MDIX bit is read/write and can be configured

 

 

 

 

manually.

4

MDIX_CM

RO

0

Auto-Switching Complete

 

 

 

 

When set, indicates that the auto-switching sequence has completed.

 

 

 

 

If 0, it indicates that the sequence has not completed or that

 

 

 

 

auto-switching is disabled.

3:0

MDIX_SD

R/W

0x0

Auto-Switching Seed

 

 

 

 

This field provides the initial seed for the switching algorithm. This seed

 

 

 

 

directly affects the number of attempts [5,4] respectively to write bits

 

 

 

 

[3:0].

A 0 sets the seed to 0x5.

472

November 16, 2008

Preliminary

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