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LM3S6965 Microcontroller

Register 23: Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address 0x11

This register provides the means for controlling and observing the events which trigger a PHY layer interrupt in the MACRIS register. This register can also be used in a polling mode via the Media Independent Interface as a means to observe key events within the PHY layer via one register address. Bits 0 through 7 are status bits which are each set based on an event. These bits are clearedaftertheregisterisread. Bits8through15ofthisregister,whenset,enablethecorresponding bit in the lower byte to signal a PHY layer interrupt in the MACRIS register.

Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17)

Base 0x4004.8000

Address 0x11

Type R/W, reset 0x0000

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

JABBER_IE RXER_IE

PRX_IE

PDF_IE

LPACK_IELSCHG_IE RFAULT_IE ANEGCOMP_IEJABBER_INTRXER_INT PRX_INT

PDF_INT LPACK_INT LSCHG_INT RFAULT_INTANEGCOMP_INT

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

RC

RC

RC

RC

RC

RC

RC

RC

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

15

JABBER_IE

R/W

0

Jabber Interrupt Enable

 

 

 

 

When set, this bit enables system interrupts when a Jabber condition

 

 

 

 

is detected by the Ethernet Controller.

14

RXER_IE

R/W

0

Receive Error Interrupt Enable

 

 

 

 

When set, this bit enables system interrupts when a receive error is

 

 

 

 

detected by the Ethernet Controller.

13

PRX_IE

R/W

0

Page Received Interrupt Enable

 

 

 

 

Whenset,thisbitenablessysteminterruptswhenanewpageisreceived

 

 

 

 

by the Ethernet Controller.

12

PDF_IE

R/W

0

Parallel Detection Fault Interrupt Enable

 

 

 

 

When set, this bit enables system interrupts when a Parallel Detection

 

 

 

 

Fault is detected by the Ethernet Controller.

11

LPACK_IE

R/W

0

LP Acknowledge Interrupt Enable

 

 

 

 

When set, this bit enables system interrupts when FLP bursts are

 

 

 

 

received with the ACK bit in the MR5 register during auto-negotiation.

10

LSCHG_IE

R/W

0

Link Status Change Interrupt Enable

 

 

 

 

Whenset,thisbitenablessysteminterruptswhenthelinkstatuschanges

 

 

 

 

from OK to FAIL.

9

RFAULT_IE

R/W

0

Remote Fault Interrupt Enable

 

 

 

 

When set, this bit enables system interrupts when a remote fault

 

 

 

 

condition is signaled by the link partner.

8

ANEGCOMP_IE

R/W

0

Auto-Negotiation Complete Interrupt Enable

 

 

 

 

When set, this bit enables system interrupts when the auto-negotiation

 

 

 

 

sequence has completed successfully.

November 16, 2008

467

Preliminary

Ethernet Controller

Bit/Field

Name

Type

Reset

Description

7

JABBER_INT

RC

0

Jabber Event Interrupt

 

 

 

 

When set, this bit indicates that a Jabber event has been detected by

 

 

 

 

the 10BASE-T circuitry.

6

RXER_INT

RC

0

Receive Error Interrupt

 

 

 

 

When set, this bit indicates that a receive error has been detected by

 

 

 

 

the Ethernet Controller.

5

PRX_INT

RC

0

Page Receive Interrupt

 

 

 

 

Whenset,thisbitindicatesthatanewpagehasbeenreceivedfromthe

 

 

 

 

link partner during auto-negotiation.

4

PDF_INT

RC

0

Parallel Detection Fault Interrupt

 

 

 

 

When set, this bit indicates that a parallel detection fault has been

 

 

 

 

detectedbytheEthernetControllerduringtheauto-negotiationprocess.

3

LPACK_INT

RC

0

LP Acknowledge Interrupt

 

 

 

 

When set, this bit indicates that an FLP burst has been received with

 

 

 

 

the ACK bit set in the MR5 register during auto-negotiation.

2

LSCHG_INT

RC

0

Link Status Change Interrupt

 

 

 

 

When set, this bit indicates that the link status has changed from OK to

 

 

 

 

FAIL.

1

RFAULT_INT

RC

0

Remote Fault Interrupt

 

 

 

 

When set, this bit indicates that a remote fault condition has been

 

 

 

 

signaled by the link partner.

0

ANEGCOMP_INT

RC

0

Auto-Negotiation Complete Interrupt

 

 

 

 

When set, this bit indicates that the auto-negotiation sequence has

 

 

 

 

completed successfully.

468

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 24: Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12

This register enables software to diagnose the results of the previous auto-negotiation.

Ethernet PHY Management Register 18 – Diagnostic (MR18)

Base 0x4004.8000

Address 0x12

Type RO, reset 0x0000

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

reserved

 

ANEGF

DPLX

RATE

RXSD

RX_LOCK

 

 

 

reserved

 

 

 

Type

RO

RO

RO

RC

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

15:13

reserved

RO

0x0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

12

ANEGF

RC

0

Auto-Negotiation Failure

 

 

 

 

Whenset,thisbitindicatesthatnocommontechnologywasfoundduring

 

 

 

 

auto-negotiation and auto-negotiation has failed. This bit remains set

 

 

 

 

until read.

11

DPLX

RO

0

Duplex Mode

 

 

 

 

When set, this bit indicates that Full-Duplex was the highest common

 

 

 

 

denominator found during the auto-negotiation process. Otherwise,

 

 

 

 

Half-Duplex was the highest common denominator found.

10

RATE

RO

0

Rate

 

 

 

 

When set, this bit indicates that 100BASE-TX was the highest common

 

 

 

 

denominator found during the auto-negotiation process. Otherwise,

 

 

 

 

10BASE-T was the highest common denominator found.

9

RXSD

RO

0

Receive Detection

 

 

 

 

When set, this bit indicates that receive signal detection has occurred

 

 

 

 

(in 100BASE-TX mode) or that Manchester-encoded data has been

 

 

 

 

detected (in 10BASE-T mode).

8

RX_LOCK

RO

0

Receive PLL Lock

 

 

 

 

When set, this bit indicates that the Receive PLL has locked onto the

 

 

 

 

receive signal for the selected speed of operation (10BASE-T or

 

 

 

 

100BASE-TX).

7:0

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

November 16, 2008

469

Preliminary

Ethernet Controller

Register 25: Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13

This register enables software to set the gain of the transmit output to compensate for transformer loss.

Ethernet PHY Management Register 19 – Transceiver Control (MR19)

Base 0x4004.8000

Address 0x13

Type R/W, reset 0x4000

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

TXO

 

 

 

 

 

 

reserved

 

 

 

 

 

 

Type

R/W

R/W

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

15:14

TXO

R/W

0x1

Transmit Amplitude Selection

 

 

 

 

The TXO field sets the transmit output amplitude to account for transmit

 

 

 

 

transformer insertion loss.

 

 

 

 

Value

Description

 

 

 

 

0x0

Gain set for 0.0dB of insertion loss

 

 

 

 

0x1

Gain set for 0.4dB of insertion loss

 

 

 

 

0x2

Gain set for 0.8dB of insertion loss

 

 

 

 

0x3

Gain set for 1.2dB of insertion loss

13:0

reserved

RO

0x000

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

470

November 16, 2008

Preliminary

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