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LM3S6965 Microcontroller

Register 20: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability (MR5), address 0x05

Thisregisterprovidestheadvertisedabilitiesofthelinkpartner’sEthernetControllerthatarereceived and stored during auto-negotiation.

Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability (MR5)

Base 0x4004.8000

Address 0x05

Type RO, reset 0x0000

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

NP

ACK

RF

 

 

 

 

A[7:0]

 

 

 

 

 

S

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

 

15

NP

RO

0

Next Page

 

 

 

 

 

When set, this bit indicates that the link partner’s Ethernet Controller is

 

 

 

 

capable of Next page exchanges to provide more detailed information

 

 

 

 

on the Ethernet Controller’s capabilities.

14

ACK

RO

0

Acknowledge

 

 

 

 

Whenset,thisbitindicatesthattheEthernetControllerhassuccessfully

 

 

 

 

received the link partner’s advertised abilities during auto-negotiation.

13

RF

RO

0

Remote Fault

 

 

 

 

Used as a standard transport mechanism for transmitting simple fault

 

 

 

 

information from the link partner.

12:5

A[7:0]

RO

0x00

Technology Ability Field

 

 

 

 

The A[7:0] field encodes individual technologies that are supported

 

 

 

 

by the Ethernet Controller. See the MR4 register for definitions. Note

 

 

 

 

that bits 12:9 describe functions that are not implemented on the

 

 

 

 

Stellaris® Ethernet Controller. Refer to the IEEE 802.3 standard for

 

 

 

 

definitions.

 

4:0

S

RO

0x00

Selector Field

 

 

 

 

The S field encodes possible messages for communicating between

 

 

 

 

Ethernet Controllers.

 

 

 

 

Value

Description

 

 

 

 

0x00

Reserved

0x01 IEEE Std 802.3

0x02 IEEE Std 802.9 ISLAN-16T

0x03 IEEE Std 802.5

0x04 IEEE Std 1394

0x05–0x1F Reserved

November 16, 2008

463

Preliminary

Ethernet Controller

Register 21: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address 0x06

This register enables software to determine the auto-negotiation and next page capabilities of the Ethernet Controller and the link partner after auto-negotiation.

Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6)

Base 0x4004.8000

Address 0x06

Type RO, reset 0x0000

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

reserved

 

 

 

 

 

PDF

LPNPA

reserved

PRX

LPANEGA

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RC

RO

RO

RC

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

15:5

reserved

RO

0x000

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

4

PDF

RC

0

Parallel Detection Fault

 

 

 

 

When set, this bit indicates that more than one technology has been

 

 

 

 

detected at link up. This bit is cleared when read.

3

LPNPA

RO

0

Link Partner is Next Page Able

 

 

 

 

When set, this bit indicates that the link partner is enabled to support

 

 

 

 

next page.

2

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

1

PRX

RC

0

New Page Received

 

 

 

 

Whenset,thisbitindicatesthatanewpagehasbeenreceivedfromthe

 

 

 

 

link partner and stored. This bit remains set until the register is read.

0

LPANEGA

RO

0

Link Partner is Auto-Negotiation Able

 

 

 

 

When set, this bit indicates that the link partner is enabled to support

 

 

 

 

auto-negotiation.

464

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register22:EthernetPHYManagementRegister16 – Vendor-Specific(MR16), address 0x10

This register enables software to configure the operation of vendor-specific modes of the Ethernet Controller.

Ethernet PHY Management Register 16 – Vendor-Specific (MR16)

Base 0x4004.8000

Address 0x10

Type R/W, reset 0x0140

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

RPTR

INPOL

reserved

TXHIM

SQEI

NL10

 

reserved

 

APOL

RVSPOL

reserved

PCSBP

RXCC

Type

R/W

R/W0

RO

R/W

R/W

R/W

RO

RO

RO

RO

R/W

R/W

RO

RO

R/W

R/W

Reset

0

0

0

0

0

0

0

1

0

1

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

15

RPTR

R/W

0

Repeater Mode

 

 

 

 

Whenset,thisbitenablestherepeatermodeofoperation. Inthismode,

 

 

 

 

full-duplex is not allowed and the Carrier Sense signal only responds

 

 

 

 

to receive activity.

14

INPOL

R/W0

0

Interrupt Polarity

 

 

 

 

Value Description

 

 

 

 

1 Sets the polarity of the PHY interrupt to be active High.

 

 

 

 

0 Sets the polarity of the PHY interrupt to active Low.

 

 

 

 

Important: Because the Media Access Controller expects active

 

 

 

 

Low interrupts from the PHY, this bit must always be

 

 

 

 

written with a 0 to ensure proper operation.

13

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

12

TXHIM

R/W

0

Transmit High Impedance Mode

 

 

 

 

Whenset,thisbitenablesthetransmitterHighImpedancemode. Inthis

 

 

 

 

mode,the TXOP and TXON transmitterpinsareputintoahighimpedance

 

 

 

 

state. The RXIP and RXIN pins remain fully functional.

11

SQEI

R/W

0

SQE Inhibit Testing

 

 

 

 

When set, this bit prohibits 10BASE-T SQE testing.

 

 

 

 

Whenclear,theSQEtestingisperformedbygeneratingacollisionpulse

 

 

 

 

following the completion of the transmission of a frame.

10

NL10

R/W

0

Natural Loopback Mode

 

 

 

 

When set, this bit enables the 10BASE-T Natural Loopback mode. In

 

 

 

 

this mode, the transmission data received by the Ethernet Controller is

 

 

 

 

looped back onto the receive data path when 10BASE-T mode is

 

 

 

 

enabled.

9:6

reserved

RO

0x5

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

November 16, 2008

465

Preliminary

Ethernet Controller

Bit/Field

Name

Type

Reset

Description

5

APOL

R/W

0

Auto-Polarity Disable

 

 

 

 

Whenset,thisbitdisablestheEthernetController’sauto-polarityfunction.

 

 

 

 

If this bit is clear, the Ethernet Controller automatically inverts the

 

 

 

 

received signal due to a wrong polarity connection during

 

 

 

 

auto-negotiation when in 10BASE-T mode.

4

RVSPOL

R/W

0

Receive Data Polarity

 

 

 

 

This bit indicates whether the receive data pulses are being inverted.

 

 

 

 

If the APOL bit is 0, then the RVSPOL bit is read-only and indicates

 

 

 

 

whether the auto-polarity circuitry is reversing the polarity. In this case,

 

 

 

 

if RVSPOL is set, it indicates that the receive data is inverted; if RVSPOL

 

 

 

 

is clear, it indicates that the receive data is not inverted.

 

 

 

 

If the APOL bit is 1, then the RVSPOL bit is writable and software can

 

 

 

 

force the receive data to be inverted. Setting RVSPOL to 1 forces the

 

 

 

 

receivedatatobeinverted;clearing RVSPOL doesnotinvertthereceive

 

 

 

 

data.

3:2

reserved

RO

0x0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

1

PCSBP

R/W

0

PCS Bypass

 

 

 

 

When set, this bit enables the bypass of the PCS and

 

 

 

 

scrambling/descrambling functions in 100BASE-TX mode. This mode

 

 

 

 

is only valid when auto-negotiation is disabled and 100BASE-TX mode

 

 

 

 

is enabled.

0

RXCC

R/W

0

Receive Clock Control

 

 

 

 

Whenset,thisbitenablestheReceiveClockControlpowersavingmode

 

 

 

 

iftheEthernetControllerisconfiguredin100BASE-TXmode. Thismode

 

 

 

 

shuts down the receive clock when no data is being received to save

 

 

 

 

power. This mode should not be used when PCSBP is enabled and is

 

 

 

 

automatically disabled when the LOOPBK bit in the MR0 register is set.

466

November 16, 2008

Preliminary

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