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LM3S6965 Microcontroller

Register 17: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02

This register, along with MR3, provides a 32-bit value indicating the manufacturer, model, and revision information.

Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2)

Base 0x4004.8000

Address 0x02

Type RO, reset 0x000E

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

OUI[21:6]

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

0

Bit/Field

Name

Type

Reset

Description

15:0

OUI[21:6]

RO

0x000E

Organizationally Unique Identifier[21:6]

 

 

 

 

This field, along with the OUI[5:0] field in MR3, makes up the

 

 

 

 

Organizationally Unique Identifier indicating the PHY manufacturer.

November 16, 2008

459

Preliminary

Ethernet Controller

Register 18: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03

This register, along with MR2, provides a 32-bit value indicating the manufacturer, model, and revision information.

Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3)

Base 0x4004.8000

Address 0x03

Type RO, reset 0x7237

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

OUI[5:0]

 

 

 

 

MN

 

 

 

 

 

RN

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

1

1

1

0

0

1

0

0

0

1

1

0

1

1

1

Bit/Field

Name

Type

Reset

Description

15:10

OUI[5:0]

RO

0x1C

Organizationally Unique Identifier[5:0]

 

 

 

 

This field, along with the OUI[21:6] field in MR2, makes up the

 

 

 

 

Organizationally Unique Identifier indicating the PHY manufacturer.

9:4

MN

RO

0x23

Model Number

 

 

 

 

The MN field represents the Model Number of the PHY.

3:0

RN

RO

0x7

Revision Number

 

 

 

 

TheRN fieldrepresentstheRevisionNumberofthePHYimplementation.

460

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 19: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address 0x04

ThisregisterprovidestheadvertisedabilitiesoftheEthernetControllerusedduringauto-negotiation. Bits 8:5 represent the Technology Ability Field bits. This field can be overwritten by software to auto-negotiate to an alternate common technology. Writing to this register has no effect until auto-negotiation is re-initiated by setting the RANEG bit in the MR0 register.

Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4)

Base 0x4004.8000

Address 0x04

Type R/W, reset 0x01E1

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

NP

reserved

RF

 

reserved

 

A3

A2

A1

A0

 

 

S

 

 

Type

RO

RO

R/W

RO

RO

RO

RO

R/W

R/W

R/W

R/W

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

Bit/Field

Name

Type

Reset

Description

15

NP

RO

0

Next Page

 

 

 

 

When set, this bit indicates the Ethernet Controller is capable of Next

 

 

 

 

PageexchangestoprovidemoredetailedinformationonthePHYlayer’s

 

 

 

 

capabilities.

14

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

13

RF

R/W

0

Remote Fault

 

 

 

 

When set, this bit indicates to the link partner that a Remote Fault

 

 

 

 

condition has been encountered.

12:9

reserved

RO

0x0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

8

A3

R/W

1

Technology Ability Field[3]

 

 

 

 

When set, this bit indicates that the Ethernet Controller supports the

 

 

 

 

100Base-TX full-duplex signaling protocol. If software wants to ensure

 

 

 

 

that this mode is not used, this bit can be cleared and auto-negotiation

 

 

 

 

re-initiated with the RANEG bit in the MR0 register.

7

A2

R/W

1

Technology Ability Field[2]

 

 

 

 

When set, this bit indicates that the Ethernet Controller supports the

 

 

 

 

100Base-TX half-duplex signaling protocol. If software wants to ensure

 

 

 

 

that this mode is not used, this bit can be cleared and auto-negotiation

 

 

 

 

re-initiated with the RANEG bit in the MR0 register.

6

A1

R/W

1

Technology Ability Field[1]

 

 

 

 

When set, this bit indicates that the Ethernet Controller supports the

 

 

 

 

10BASE-T full-duplex signaling protocol. If software wants to ensure

 

 

 

 

that this mode is not used, this bit can be cleared and auto-negotiation

 

 

 

 

re-initiated with the RANEG bit in the MR0 register..

November 16, 2008

461

Preliminary

Ethernet Controller

Bit/Field

Name

Type

Reset

Description

5

A0

R/W

1

Technology Ability Field[0]

 

 

 

 

When set, this bit indicates that the Ethernet Controller supports the

 

 

 

 

10BASE-T half-duplex signaling protocol. If software wants to ensure

 

 

 

 

that this mode is not used, this bit can be cleared and auto-negotiation

 

 

 

 

re-initiated with the RANEG bit in the MR0 register..

4:0

S

RO

0x1

Selector Field

 

 

 

 

The S field encodes 32 possible messages for communicating between

Ethernet Controllers. This field is hard-coded to 0x01, indicating that the Stellaris® Ethernet Controller is IEEE 802.3 compliant.

462

November 16, 2008

Preliminary

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