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Ethernet Controller

Register 14: Ethernet MAC Transmission Request (MACTR), offset 0x038

This register enables software to initiate the transmission of the frame currently located in the TX FIFO. Once the frame has been transmitted from the TX FIFO or a transmission error has been encountered, the NEWTX bit is automatically cleared.

Ethernet MAC Transmission Request (MACTR)

Base 0x4004.8000

Offset 0x038

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

NEWTX

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:1

reserved

RO

0x0000.000

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

0

NEWTX

R/W

0

New Transmission

 

 

 

 

When set, the NEWTX bit initiates an Ethernet transmission once the

packet has been placed in the TX FIFO. This bit is cleared once the transmission has been completed. If early transmission is being used (see the MACTHR register), this bit does not need to be set.

16.6MII Management Register Descriptions

The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY layer. The registers are collectively known as the MII Management registers. All addresses given are absolute. Addresses not listed are reserved; these addresses should not be written to and any data read should be ignored. Also see “Ethernet MAC Register Descriptions” on page 436.

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November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 15: Ethernet PHY Management Register 0 – Control (MR0), address 0x00

This register enables software to configure the operation of the PHY layer. The default settings of theseregistersaredesignedtoinitializetheEthernetControllertoanormaloperationalmodewithout configuration.

Ethernet PHY Management Register 0 – Control (MR0)

Base 0x4004.8000

Address 0x00

Type R/W, reset 0x3100

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

RESET

LOOPBK SPEEDSL ANEGEN

PWRDN

ISO

RANEG

DUPLEX

COLT

 

 

 

reserved

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

1

1

0

0

0

1

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

15

RESET

R/W

0

Reset Registers

 

 

 

 

When set, this bit resets the PHY layer registers to their default state

 

 

 

 

and reinitializes internal state machines. Once the reset operation has

 

 

 

 

completed, this bit is cleared by hardware.

14

LOOPBK

R/W

0

Loopback Mode

 

 

 

 

Whenset,thisbitenablestheLoopbackmodeofoperation. Thereceiver

 

 

 

 

ignores external inputs and receives the data that is transmitted by the

 

 

 

 

transmitter.

13

SPEEDSL

R/W

1

Speed Select

 

 

 

 

Value Description

 

 

 

 

1 Enables the 100 Mb/s mode of operation (100BASE-TX).

 

 

 

 

0 Enables the 10 Mb/s mode of operation (10BASE-T).

12

ANEGEN

R/W

1

Auto-Negotiation Enable

 

 

 

 

When set, this bit enables the auto-negotiation process.

11

PWRDN

R/W

0

Power Down

 

 

 

 

When set, this bit places the PHY layer into a low-power consuming

 

 

 

 

state. All data on the data inputs is ignored.

10

ISO

R/W

0

Isolate

 

 

 

 

When set, this bit isolates the transmit and receive data paths and

 

 

 

 

ignores all data being transmitted and received.

9

RANEG

R/W

0

Restart Auto-Negotiation

 

 

 

 

Whenset,thisbitrestartstheauto-negotiationprocess. Oncetherestart

 

 

 

 

has initiated, this bit is cleared by hardware.

November 16, 2008

455

Preliminary

Ethernet Controller

Bit/Field

Name

Type

Reset

Description

8

DUPLEX

R/W

1

Set Duplex Mode

 

 

 

 

Value

Description

 

 

 

 

1

Enables the Full-Duplex mode of operation. This bit can be

 

 

 

 

 

set by software in a manual configuration process or by the

 

 

 

 

 

auto-negotiation process.

 

 

 

 

0

Enables the Half-Duplex mode of operation.

7

COLT

R/W

0

Collision Test

 

 

 

 

When set, this bit enables the Collision Test mode of operation. The

 

 

 

 

COLT bit is set after the initiation of a transmission and is cleared once

 

 

 

 

the transmission is halted.

6:0

reserved

R/W

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

These bits should always be written as zero.

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November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 16: Ethernet PHY Management Register 1 – Status (MR1), address 0x01

This register enables software to determine the capabilities of the PHY layer and perform its initialization and operation appropriately.

Ethernet PHY Management Register 1 – Status (MR1)

Base 0x4004.8000

Address 0x01

Type RO, reset 0x7849

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

reserved 100X_F 100X_H

10T_F

10T_H

 

reserved

 

MFPS

ANEGC

RFAULT

ANEGA

LINK

JAB

EXTD

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RC

RO

RO

RC

RO

Reset

0

1

1

1

1

0

0

0

0

1

0

0

1

0

0

1

Bit/Field

Name

Type

Reset

Description

15

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

14

100X_F

RO

1

100BASE-TX Full-Duplex Mode

 

 

 

 

When set, this bit indicates that the Ethernet Controller is capable of

 

 

 

 

supporting 100BASE-TX Full-Duplex mode.

13

100X_H

RO

1

100BASE-TX Half-Duplex Mode

 

 

 

 

When set, this bit indicates that the Ethernet Controller is capable of

 

 

 

 

supporting 100BASE-TX Half-Duplex mode.

12

10T_F

RO

1

10BASE-T Full-Duplex Mode

 

 

 

 

When set, this bit indicates that the Ethernet Controller is capable of

 

 

 

 

10BASE-T Full-Duplex mode.

11

10T_H

RO

1

10BASE-T Half-Duplex Mode

 

 

 

 

When set, this bit indicates that the Ethernet Controller is capable of

 

 

 

 

supporting 10BASE-T Half-Duplex mode.

10:7

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

6

MFPS

RO

1

Management Frames with Preamble Suppressed

 

 

 

 

When set, this bit indicates that the Management Interface is capable

 

 

 

 

of receiving management frames with the preamble suppressed.

5

ANEGC

RO

0

Auto-Negotiation Complete

 

 

 

 

When set, this bit indicates that the auto-negotiation process has been

 

 

 

 

completed and that the extended registers defined by the

 

 

 

 

auto-negotiation protocol are valid.

4

RFAULT

RC

0

Remote Fault

 

 

 

 

When set, this bit indicates that a remote fault condition has been

detected. This bit remains set until it is read, even if the condition no longer exists.

November 16, 2008

457

Preliminary

Ethernet Controller

Bit/Field

Name

Type

Reset

Description

3

ANEGA

RO

1

Auto-Negotiation

 

 

 

 

When set, this bit indicates that the Ethernet Controller has the ability

 

 

 

 

to perform auto-negotiation.

2

LINK

RO

0

Link Made

 

 

 

 

When set, this bit indicates that a valid link has been established by the

 

 

 

 

Ethernet Controller.

1

JAB

RC

0

Jabber Condition

 

 

 

 

When set, this bit indicates that a jabber condition has been detected

 

 

 

 

by the Ethernet Controller. This bit remains set until it is read, even if

 

 

 

 

the jabber condition no longer exists.

0

EXTD

RO

1

Extended Capabilities

 

 

 

 

When set, this bit indicates that the Ethernet Controller provides an

 

 

 

 

extended set of capabilities that can be accessed through the extended

 

 

 

 

register set.

458

November 16, 2008

Preliminary

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