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LM3S6965 Microcontroller

Register 6: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014

This register enables software to program the first four bytes of the hardware MAC address of the Network Interface Card (NIC). (The last two bytes are in MACIA1). The 6-byte Individual Address iscomparedagainsttheincomingDestinationAddressfieldstodeterminewhethertheframeshould be received.

Ethernet MAC Individual Address 0 (MACIA0)

Base 0x4004.8000

Offset 0x014

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

MACOCT4

 

 

 

 

 

 

MACOCT3

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

MACOCT2

 

 

 

 

 

 

MACOCT1

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:24

MACOCT4

R/W

0x00

MAC Address Octet 4

 

 

 

 

The MACOCT4 bits represent the fourth octet of the MAC address used

 

 

 

 

to uniquely identify the Ethernet Controller.

23:16

MACOCT3

R/W

0x00

MAC Address Octet 3

 

 

 

 

The MACOCT3 bits represent the third octet of the MAC address used

 

 

 

 

to uniquely identify the Ethernet Controller.

15:8

MACOCT2

R/W

0x00

MAC Address Octet 2

 

 

 

 

The MACOCT2 bitsrepresentthesecondoctetoftheMACaddressused

 

 

 

 

to uniquely identify the Ethernet Controller.

7:0

MACOCT1

R/W

0x00

MAC Address Octet 1

 

 

 

 

The MACOCT1 bits represent the first octet of the MAC address used to

 

 

 

 

uniquely identify the Ethernet Controller.

November 16, 2008

445

Preliminary

Ethernet Controller

Register 7: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018

This register enables software to program the last two bytes of the hardware MAC address of the Network Interface Card (NIC). (The first four bytes are in MACIA0). The 6-byte IAR is compared againsttheincomingDestinationAddressfieldstodeterminewhethertheframeshouldbereceived.

Ethernet MAC Individual Address 1 (MACIA1)

Base 0x4004.8000

Offset 0x018

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

MACOCT6

 

 

 

 

 

 

MACOCT5

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:16

reserved

RO

0x0000

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

15:8

MACOCT6

R/W

0x00

MAC Address Octet 6

 

 

 

 

The MACOCT6 bits represent the sixth octet of the MAC address used

 

 

 

 

to uniquely identify each Ethernet Controller.

7:0

MACOCT5

R/W

0x00

MAC Address Octet 5

 

 

 

 

The MACOCT5 bits represent the fifth octet of the MAC address used to

 

 

 

 

uniquely identify the Ethernet Controller.

446

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 8: Ethernet MAC Threshold (MACTHR), offset 0x01C

In order to increase the transmission rate, it is possible to program the Ethernet Controller to begin transmissionofthenextframepriortothecompletionofthetransmissionofthecurrentframe. Note: Extreme care must be used when implementing this function. Software must be able to guarantee that the complete frame is able to be stored in the transmission FIFO prior to the completion of the transmission frame.

This register enables software to set the threshold level at which the transmission of the frame begins. If the THRESH bits are set to 0x3F, which is the reset value, the early transmission feature is disabled, and transmission does not start until the NEWTX bit is set in the MACTR register.

Writing the THRESH bits to any value besides 0x3F enables the early transmission feature. Once the byte count of data in the TX FIFO reaches the value derived from the THRESH bits as shown below, transmission of the frame begins. When THRESH is set to all 0s, transmission of the frame begins after 4 bytes (a single write) are stored in the TX FIFO. Each increment of the THRESH bit field waits for an additional 32 bytes of data (eight writes) to be stored in the TX FIFO. Therefore, a value of 0x01 causes the transmitter to wait for 36 bytes of data to be written while a value of 0x02 makes the wait equal to 68 bytes of written data. In general, early transmission starts when:

Number of Bytes >= 4 (THRESH x 8 + 1)

Reaching the threshold level has the same effect as setting the NEWTX bit in the MACTR register. Transmission of the frame begins and then the number of bytes indicated by the Data Length field is transmitted. Because under-run checking is not performed, if any event, such as an interrupt, delays the filling of the FIFO, the tail pointer may reach and pass the write pointer in the TX FIFO. In this event, indeterminate values are transmitted rather than the end of the frame. Therefore, sufficient bus bandwidth for writing to the TX FIFO must be guaranteed by the software.

If a frame smaller than the threshold level must be sent, the NEWTX bit in the MACTR register must be set with an explicit write. This initiates the transmission of the frame even though the threshold limit has not been reached.

If the threshold level is set too small, it is possible for the transmitter to underrun. If this occurs, the transmit frame is aborted, and a transmit error occurs. Note that in this case, the TXER bit in the MACRIS is not set meaning that the CPU receives no indication that a transmit error happened.

Ethernet MAC Threshold (MACTHR)

Base 0x4004.8000

Offset 0x01C

Type R/W, reset 0x0000.003F

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

reserved

 

 

 

 

 

 

THRESH

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

Bit/Field

Name

Type

Reset

Description

31:6

reserved

RO

0x0000.00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

November 16, 2008

447

Preliminary

Ethernet Controller

Bit/Field

Name

Type

Reset

Description

5:0

THRESH

R/W

0x3F

Threshold Value

 

 

 

 

TheTHRESH bitsrepresenttheearlytransmitthreshold.Oncetheamount

 

 

 

 

of data in the TX FIFO exceeds the value represented by the above

 

 

 

 

equation, transmission of the packet begins.

448

November 16, 2008

Preliminary

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