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Ethernet Controller

Register 2: Ethernet MAC Interrupt Mask (MACIM), offset 0x004

This register allows software to enable/disable Ethernet MAC interrupts. Clearing a bit disables the interrupt, while setting the bit enables it.

Ethernet MAC Interrupt Mask (MACIM)

Base 0x4004.8000

Offset 0x004

Type R/W, reset 0x0000.007F

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

reserved

 

 

 

 

PHYINTM MDINTM

RXERM

FOVM

TXEMPM

TXERM

RXINTM

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

Bit/Field

Name

Type

Reset

Description

31:7

reserved

RO

0x0000.00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

6

PHYINTM

R/W

1

Mask PHY Interrupt

 

 

 

 

Clearing this bit masks the PHYINT bit in the MACRIS register from

 

 

 

 

being set.

5

MDINTM

R/W

1

Mask MII Transaction Complete

 

 

 

 

Clearingthisbitmasksthe MDINT bitinthe MACRIS registerfrombeing

 

 

 

 

set.

4

RXERM

R/W

1

Mask Receive Error

 

 

 

 

Clearing this bit masks the RXER bit in the MACRIS register from being

 

 

 

 

set.

3

FOVM

R/W

1

Mask FIFO Overrun

 

 

 

 

Clearing this bit masks the FOV bit in the MACRIS register from being

 

 

 

 

set.

2

TXEMPM

R/W

1

Mask Transmit FIFO Empty

 

 

 

 

Clearingthisbitmasksthe TXEMP bitinthe MACRIS registerfrombeing

 

 

 

 

set.

1

TXERM

R/W

1

Mask Transmit Error

 

 

 

 

Clearing this bit masks the TXER bit in the MACRIS register from being

 

 

 

 

set.

0

RXINTM

R/W

1

Mask Packet Received

 

 

 

 

Clearingthisbitmasksthe RXINT bitinthe MACRIS registerfrombeing

 

 

 

 

set.

440

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 3: Ethernet MAC Receive Control (MACRCTL), offset 0x008

This register configures the receiver and controls the types of frames that are received.

It is important to note that when the receiver is enabled, all valid frames with a broadcast address of FF-FF-FF-FF-FF-FF in the Destination Address field are received and stored in the RX FIFO, even if the AMUL bit is not set.

Ethernet MAC Receive Control (MACRCTL)

Base 0x4004.8000

Offset 0x008

Type R/W, reset 0x0000.0008

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

reserved

 

 

 

 

 

RSTFIFO BADCRC

PRMS

AMUL

RXEN

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

Bit/Field

Name

Type

Reset

Description

31:5

reserved

RO

0x0000.000

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

4

RSTFIFO

R/W

0

Clear Receive FIFO

 

 

 

 

When set, this bit clears the receive FIFO. This should be done when

 

 

 

 

software initialization is performed.

 

 

 

 

It is recommended that the receiver be disabled (RXEN = 0), before a

 

 

 

 

reset is initiated (RSTFIFO = 1). This sequence flushes and resets the

 

 

 

 

RX FIFO.

 

 

 

 

This bit is automatically cleared when read.

3

BADCRC

R/W

1

Enable Reject Bad CRC

 

 

 

 

When set, the BADCRC bit enables the rejection of frames with an

 

 

 

 

incorrectly calculated CRC. If a bad CRC is encountered, the RXER bit

 

 

 

 

in the MACRIS register is set and the receiver FIFO is reset.

2

PRMS

R/W

0

Enable Promiscuous Mode

 

 

 

 

When set, the PRMS bit enables Promiscuous mode, which accepts all

 

 

 

 

valid frames, regardless of the specified Destination Address.

1

AMUL

R/W

0

Enable Multicast Frames

 

 

 

 

When set, the AMUL bit enables the reception of multicast frames.

0

RXEN

R/W

0

Enable Receiver

 

 

 

 

When set the RXEN bit enables the Ethernet receiver. When this bit is

 

 

 

 

clear, the receiver is disabled and all frames are ignored.

November 16, 2008

441

Preliminary

Ethernet Controller

Register 4: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C

This register configures the transmitter and controls the frames that are transmitted.

Ethernet MAC Transmit Control (MACTCTL)

Base 0x4004.8000

Offset 0x00C

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

reserved

 

 

 

 

 

DUPLEX

reserved

CRC

PADEN

TXEN

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

RO

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:5

reserved

RO

0x0000.000

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

4

DUPLEX

R/W

0

Enable Duplex Mode

 

 

 

 

When set, this bit enables Duplex mode, allowing simultaneous

 

 

 

 

transmission and reception.

3

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

2

CRC

R/W

0

Enable CRC Generation

 

 

 

 

When set this bit enables the automatic generation of the CRC and its

 

 

 

 

placement at the end of the packet. If this bit is clear, the frames placed

 

 

 

 

in the TX FIFO are sent exactly as they are written into the FIFO.

 

 

 

 

Note that this bit should generally be set.

1

PADEN

R/W

0

Enable Packet Padding

 

 

 

 

When set, this bit enables the automatic padding of packets that do not

 

 

 

 

meet the minimum frame size.

 

 

 

 

Note that this bit should generally be set.

0

TXEN

R/W

0

Enable Transmitter

 

 

 

 

When set, this bit enables the transmitter. When this bit is clear, the

 

 

 

 

transmitter is disabled.

442

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 5: Ethernet MAC Data (MACDATA), offset 0x010

This register enables software to access the TX and RX FIFOs.

Reads from this register return the data stored in the RX FIFO from the location indicated by the read pointer. The read pointer is then auto incremented to the next RX FIFO location. Reading from the RX FIFO when a frame has not been received or is in the process of being received will return indeterminate data and not increment the read pointer.

Writes to this register store the data in the TX FIFO at the location indicated by the write pointer. The write pointer is the auto incremented to the next TX FIFO location. Writing more data into the TX FIFO than indicated in the length field will result in the data being lost. Writing less data into the TX FIFO than indicated in the length field will result in indeterminate data being appended to the endoftheframetoachievetheindicatedlength. AttemptingtowritethenextframeintotheTXFIFO before transmission of the first has completed will result in the data being lost.

There is no mechanism for randomly accessing bytes in either the RX or TX FIFOs. Data must be read from the RX FIFO sequentially and stored in a buffer for further processing. Once a read has been performed, the data in the FIFO cannot be re-read. Data must be written to the TX FIFO sequentially. If an error is made in placing the frame into the TX FIFO, the write pointer can be reset to the start of the TX FIFO by writing the TXER bit of the MACIACK register and then the data re-written.

Reads

Ethernet MAC Data (MACDATA)

Base 0x4004.8000

Offset 0x010

Type RO, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

RXDATA

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

RXDATA

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:0

RXDATA

RO

0x0000.0000

Receive FIFO Data

 

 

 

 

The RXDATA bitsrepresentthenextwordofdatastoredintheRXFIFO.

November 16, 2008

443

Preliminary

Ethernet Controller

Writes

Ethernet MAC Data (MACDATA)

Base 0x4004.8000

Offset 0x010

Type WO, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

TXDATA

 

 

 

 

 

 

 

Type

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

TXDATA

 

 

 

 

 

 

 

Type

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:0

TXDATA

WO

0x0000.0000

Transmit FIFO Data

 

 

 

 

The TXDATA bits represent the next word of data to place in the TX

 

 

 

 

FIFO for transmission.

444

November 16, 2008

Preliminary

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