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Ethernet Controller

Offset

Name

Type

Reset

Description

See

page

 

 

 

 

 

0x018

MACIA1

R/W

0x0000.0000

Ethernet MAC Individual Address 1

446

0x01C

MACTHR

R/W

0x0000.003F

Ethernet MAC Threshold

447

0x020

MACMCTL

R/W

0x0000.0000

Ethernet MAC Management Control

449

0x024

MACMDV

R/W

0x0000.0080

Ethernet MAC Management Divider

450

0x02C

MACMTXD

R/W

0x0000.0000

Ethernet MAC Management Transmit Data

451

0x030

MACMRXD

R/W

0x0000.0000

Ethernet MAC Management Receive Data

452

0x034

MACNP

RO

0x0000.0000

Ethernet MAC Number of Packets

453

0x038

MACTR

R/W

0x0000.0000

Ethernet MAC Transmission Request

454

MII Management

 

 

 

 

-

MR0

R/W

0x3100

Ethernet PHY Management Register 0 – Control

455

-

MR1

RO

0x7849

Ethernet PHY Management Register 1 – Status

457

-

MR2

RO

0x000E

Ethernet PHY Management Register 2 – PHY Identifier

459

1

 

 

 

 

 

-

MR3

RO

0x7237

Ethernet PHY Management Register 3 – PHY Identifier

460

2

 

 

 

 

 

-

MR4

R/W

0x01E1

EthernetPHYManagementRegister4–Auto-Negotiation

461

Advertisement

 

 

 

 

 

-

MR5

RO

0x0000

EthernetPHYManagementRegister5–Auto-Negotiation

463

Link Partner Base Page Ability

 

 

 

 

 

-

MR6

RO

0x0000

EthernetPHYManagementRegister6–Auto-Negotiation

464

Expansion

 

 

 

 

 

-

MR16

R/W

0x0140

Ethernet PHY Management Register 16 –

465

Vendor-Specific

 

 

 

 

 

-

MR17

R/W

0x0000

Ethernet PHY Management Register 17 – Interrupt

467

Control/Status

 

 

 

 

 

-

MR18

RO

0x0000

Ethernet PHY Management Register 18 – Diagnostic

469

-

MR19

R/W

0x4000

Ethernet PHY Management Register 19 – Transceiver

470

Control

 

 

 

 

 

-

MR23

R/W

0x0010

Ethernet PHY Management Register 23 – LED

471

Configuration

 

 

 

 

 

-

MR24

R/W

0x00C0

Ethernet PHY Management Register 24 –MDI/MDIX

472

Control

 

 

 

 

 

16.5Ethernet MAC Register Descriptions

The remainder of this section lists and describes the Ethernet MAC registers, in numerical order by address offset. Also see “MII Management Register Descriptions” on page 454.

436

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 1: Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000

The MACRIS/MACIACK register is the interrupt status and acknowledge register. On a read, this register gives the current status value of the corresponding interrupt prior to masking. On a write, setting any bit clears the corresponding interrupt status bit.

Reads

Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK)

Base 0x4004.8000

Offset 0x000

Type RO, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

reserved

 

 

 

 

PHYINT

MDINT

RXER

FOV

TXEMP

TXER

RXINT

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:7

reserved

RO

0x0000.00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

6

PHYINT

RO

0

PHY Interrupt

 

 

 

 

When set, indicates that an enabled interrupt in the PHY layer has

 

 

 

 

occurred. MR17 inthePHYmustbereadtodeterminethespecificPHY

 

 

 

 

event that triggered this interrupt.

5

MDINT

RO

0

MII Transaction Complete

 

 

 

 

Whenset,indicatesthatatransaction(readorwrite)ontheMIIinterface

 

 

 

 

has completed successfully.

4

RXER

RO

0

Receive Error

 

 

 

 

This bit indicates that an error was encountered on the receiver. The

 

 

 

 

possible errors that can cause this interrupt bit to be set are:

 

 

 

 

A receive error occurs during the reception of a frame (100 Mb/s

 

 

 

 

only).

 

 

 

 

The frame is not an integer number of bytes (dribble bits) due to an

 

 

 

 

alignment error.

 

 

 

 

The CRC of the frame does not pass the FCS check.

 

 

 

 

The length/type field is inconsistent with the frame data size when

 

 

 

 

interpreted as a length field.

3

FOV

RO

0

FIFO Overrun

 

 

 

 

When set, indicates that an overrun was encountered on the receive

 

 

 

 

FIFO.

November 16, 2008

437

Preliminary

Ethernet Controller

Bit/Field

Name

Type

Reset

Description

2

TXEMP

RO

0

Transmit FIFO Empty

 

 

 

 

When set, indicates that the packet was transmitted and that the TX

 

 

 

 

FIFO is empty.

1

TXER

RO

0

Transmit Error

 

 

 

 

When set, indicates that an error was encountered on the transmitter.

 

 

 

 

The possible errors that can cause this interrupt bit to be set are:

 

 

 

 

The data length field stored in the TX FIFO exceeds 2032 decimal

 

 

 

 

(bufferlength - 16bytesofheaderdata). Theframeisnotsentwhen

 

 

 

 

this error occurs.

 

 

 

 

The retransmission attempts during the backoff process have

 

 

 

 

exceeded the maximum limit of 16 decimal.

0

RXINT

RO

0

Packet Received

 

 

 

 

When set, indicates that at least one packet has been received and is

 

 

 

 

stored in the receiver FIFO.

Writes

Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK)

Base 0x4004.8000

Offset 0x000

Type WO, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

reserved

 

 

 

 

PHYINT

MDINT

RXER

FOV

TXEMP

TXER

RXINT

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

W1C

W1C

W1C

W1C

W1C

W1C

W1C

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:7

reserved

RO

0x0000.00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

6

PHYINT

W1C

0

Clear PHY Interrupt

 

 

 

 

Setting this bit clears the PHYINT interrupt in the MACRIS register.

5

MDINT

W1C

0

Clear MII Transaction Complete

 

 

 

 

Setting this bit clears the MDINT interrupt in the MACRIS register.

4

RXER

W1C

0

Clear Receive Error

 

 

 

 

Setting this bit clears the RXER interrupt in the MACRIS register.

3

FOV

W1C

0

Clear FIFO Overrun

 

 

 

 

Setting this bit clears the FOV interrupt in the MACRIS register.

438

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Bit/Field

Name

Type

Reset

Description

2

TXEMP

W1C

0

Clear Transmit FIFO Empty

 

 

 

 

Setting this bit clears the TXEMP interrupt in the MACRIS register.

1

TXER

W1C

0

Clear Transmit Error

 

 

 

 

Setting this bit clears the TXER interrupt in the MACRIS register and

 

 

 

 

resets the TX FIFO write pointer.

0

RXINT

W1C

0

Clear Packet Received

 

 

 

 

Setting this bit clears the RXINT interrupt in the MACRIS register.

November 16, 2008

439

Preliminary

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