Ethernet Controller

16.2.3.4 MDI/MDI-X Configuration

The Ethernet Controller supports the MDI/MDI-X configuration as defined in IEEE 802.3-2002 specification.TheMDI/MDI-Xconfigurationeliminatestheneedforcross-overcableswhenconnecting to another device, such as a hub. The algorithm is controlled via settings in the Ethernet PHY Management Register 24 - MDI/MIDIX Control (MR24). Refer to page 472 for additional details about these settings.

16.2.3.5 LED Indicators

The Ethernet Controller supports two LED signals that can be used to indicate various states of operation. These signals are mapped to the LED0 and LED1 pins. By default, these pins are configured as GPIO signals (PF3 and PF2). For the PHY layer to drive these signals, they must be reconfiguredtotheiralternatefunction. See“General-PurposeInput/Outputs(GPIOs)”onpage176 for additional details. The function of these pins is programmable via the PHY layer Ethernet PHY Management Register 23 - LED Configuration (MR23). Refertopage471foradditionaldetailson how to program these LED functions.

16.2.4Interrupts

The Ethernet Controller can generate an interrupt for one or more of the following conditions:

■A frame has been received into an empty RX FIFO

■A frame transmission error has occurred

■A frame has been transmitted successfully

■A frame has been received with inadequate room in the RX FIFO (overrun)

■A frame has been received with one or more error conditions (for example, FCS failed)

■An MII management transaction between the MAC and PHY layers has completed

■One or more of the following PHY layer conditions occurs:

–Auto-Negotiate Complete

–Remote Fault

–Link Status Change

–Link Partner Acknowledge

–Parallel Detect Fault

–Page Received

–Receive Error

–Jabber Event Detected

16.3Initialization and Configuration

To use the Ethernet Controller, it must be enabled by setting the EPHY0 and EMAC0 bits in the RCGC2 register (see page 121). The following steps can then be used to configure the Ethernet Controller for basic operation.

Preliminary

LM3S6965 Microcontroller

1.Program the MACDIV register to obtain a 2.5 MHz clock (or less) on the internal MII. Assuming a 20-MHz system clock, the MACDIV value should be 0x03 or greater.

2.Program the MACIA0 and MACIA1 register for address filtering.

3.Program the MACTCTL register for Auto CRC generation, padding, and full-duplex operation using a value of 0x16.

4.Programthe MACRCTL registertoflushthereceiveFIFOandrejectframeswithbadFCSusing a value of 0x18.

5.Enable both the Transmitter and Receive by setting the LSB in both the MACTCTL and MACRCTL registers.

6.Totransmitaframe,writetheframeintotheTXFIFOusingthe Ethernet MAC Data (MACDATA) register. ThensettheNEWTX bitinthe EthernetMacTransmissionRequest(MACTR) register to initiate the transmit process. When the NEWTX bit has been cleared, the TX FIFO is available for the next transmit frame.

7.To receive a frame, wait for the NPR field in the Ethernet MAC Number of Packets (MACNP) registertobenon-zero. ThenbeginreadingtheframefromtheRXFIFObyusingthe MACDATA register. When the frame (including the FCS field) has been read, the NPR field decrements by one. When there are no more frames in the RX FIFO, the NPR field reads 0.

16.4Ethernet Register Map

Table 16-2 on page 435 lists the Ethernet MAC registers. All addresses given are relative to the Ethernet MAC base address of 0x4004.8000.

The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY layer. The registers are collectively known as the MII Management registers and are detailed in Section 22.2.4 of the IEEE 802.3 specification. Table 16-2 on page 435 also lists these MII Managementregisters. All addresses given are absolute and are written directly to the REGADR field of the Ethernet MAC Management Control (MACMCTL) register. The format of registers 0 to 15 are defined by the IEEE specification and are common to all PHY layer implementations. The only varianceallowedisforfeaturesthatmayormaynotbesupportedbyaspecificPHYimplementation. Registers 16 to 31 are vendor-specific registers, used to support features that are specific to a vendor's PHY implementation. Vendor-specific registers not listed are reserved.

Table 16-2. Ethernet Register Map

Preliminary