LM3S6965 Microcontroller

16.2.2Internal MII Operation

For the MII management interface to function properly, the MDIO signal must be connected through a 10k Ω pull-up resistor to the +3.3 V supply. Failure to connect this pull-up resistor prevents managementtransactionsonthisinternalMIItofunction. Notethatitispossiblefordatatransmission across the MII to still function since the PHY layer auto-negotiates the link parameters by default.

FortheMIImanagementinterfacetofunctionproperly,theinternalclockmustbedivideddownfrom thesystemclocktoafrequencynogreaterthan2.5MHz. The Ethernet MAC Management Divider (MACMDV) register contains the divider used for scaling down the system clock. See page 450 for more details about the use of this register.

16.2.3PHY Operation

The Physical Layer (PHY) in the Ethernet Controller includes integrated ENDECs, scrambler/descrambler, dual-speed clock recovery, and full-featured auto-negotiation functions. The transmitter includes an on-chip pulse shaper and a low-power line driver. The receiver has an adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery. ThetransceiverinterfacestoCategory-5unshieldedtwistedpair(Cat-5UTP)cablingfor100BASE-TX applications, and Category-3 unshielded twisted pair (Cat-3 UTP) for 10BASE-T applications. The Ethernet Controller is connected to the line media via dual 1:1 isolation transformers. No external filter is required.

16.2.3.1 Clock Selection

The Ethernet Controller has an on-chip crystal oscillator which can also be driven by an external oscillator. In this mode of operation, a 25-MHz crystal should be connected between the XTALPPHY andXTALNPHY pins.Alternatively,anexternal25-MHzclockinputcanbeconnectedtotheXTALPPHY pin. Inthismodeofoperation,acrystalisnotrequiredandthe XTALNPHY pinmustbetiedtoground.

16.2.3.2 Auto-Negotiation

The Ethernet Controller supports the auto-negotiation functions of Clause 28 of the IEEE 802.3 standard for 10/100 Mbps operation over copper wiring. This function is controlled via register settings. The auto-negotiation function is turned on by default, and the ANEGEN bit in the Ethernet PHY Management Register 0 - Control (MR0) is set after reset. Software can disable the auto-negotiationfunctionbyclearingtheANEGEN bit.ThecontentsoftheEthernetPHYManagement Register - Auto-Negotiation Advertisement (MR4) are reflected to the Ethernet Controller’s link partner during auto-negotiation via fast-link pulse coding.

Once auto-negotiation is complete, the DPLX and RATE bits in the Ethernet PHY Management Register 18 - Diagnostic (MR18) register reflect the actual speed and duplex condition. If auto-negotiation fails to establish a link for any reason, the ANEGF bit in the MR18 register reflects this and auto-negotiation restarts from the beginning. Setting the RANEG bit in the MR0 register also causes auto-negotiation to restart.

16.2.3.3 Polarity Correction

The Ethernet Controller is capable of either automatic or manual polarity reversal for 10BASE-T andauto-negotiationfunctions. Bits4and5(RVSPOL and APOL)inthe Ethernet PHY Management Register 16 - Vendor-Specific (MR16) control this feature. The default is automatic mode, where APOL is clear and RVSPOL indicates if the detection circuitry has inverted the input signal. To enter manual mode, APOL should be set. In manual mode RVSPOL controls the signal polarity.

Preliminary