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Inter-Integrated Circuit (I2C) Interface

Figure 15-13. Slave Command Sequence

Idle

Write OWN Slave

Address to

I2CSOAR

Write -------1 to

I2CSCSR

 

 

 

Read I2CSCSR

NO

TREQ bit=1?

NO

RREQ bit=1?

 

YES

 

FBR is

YES

 

 

also valid

 

Write data to

 

Read data from

 

I2CSDR

 

I2CSDR

15.3Initialization and Configuration

The following example shows how to configure the I2C module to send a single byte as a master. This assumes the system clock is 20 MHz.

1.Enable the I2C clock by writing a value of 0x0000.1000 to the RCGC1 register in the System Control module.

2.EnabletheclocktotheappropriateGPIOmoduleviathe RCGC2 registerintheSystemControl module.

3.In the GPIO module, enable the appropriate pins for their alternate function using the GPIOAFSEL register. Also, be sure to enable the same pins for Open Drain operation.

4.Initialize the I2C Master by writing the I2CMCR register with a value of 0x0000.0020.

5.Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct value. Thevaluewrittentothe I2CMTPR registerrepresentsthenumberofsystemclockperiods in one SCL clock period. The TPR value is determined by the following equation:

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November 16, 2008

Preliminary

LM3S6965 Microcontroller

TPR = (System Clock / (2 * (SCL_LP + SCL_HP) * SCL_CLK)) - 1;

TPR = (20MHz / (2 * (6 + 4) * 100000)) - 1;

TPR = 9

Write the I2CMTPR register with the value of 0x0000.0009.

6.Specify the slave address of the master and that the next operation will be a Send by writing the I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B.

7.Place data (byte) to be sent in the data register by writing the I2CMDR register with the desired data.

8.Initiate a single byte send of the data from Master to Slave by writing the I2CMCS register with a value of 0x0000.0007 (STOP, START, RUN).

9.Wait until the transmission completes by polling the I2CMCS register’s BUSBSY bit until it has been cleared.

15.4Register Map

Table 15-2 on page 405 lists the I2C registers. All addresses given are relative to the I2C base addresses for the master and slave:

I2C Master 0: 0x4002.0000

I2C Slave 0: 0x4002.0800

I2C Master 1: 0x4002.1000

I2C Slave 1: 0x4002.1800

Table 15-2. Inter-Integrated Circuit (I2C) Interface Register Map

Offset

Name

Type

Reset

Description

See

page

 

 

 

 

 

I2C Master

 

 

 

 

 

0x000

I2CMSA

R/W

0x0000.0000

I2C Master Slave Address

407

0x004

I2CMCS

R/W

0x0000.0000

I2C Master Control/Status

408

0x008

I2CMDR

R/W

0x0000.0000

I2C Master Data

412

0x00C

I2CMTPR

R/W

0x0000.0001

I2C Master Timer Period

413

0x010

I2CMIMR

R/W

0x0000.0000

I2C Master Interrupt Mask

414

0x014

I2CMRIS

RO

0x0000.0000

I2C Master Raw Interrupt Status

415

0x018

I2CMMIS

RO

0x0000.0000

I2C Master Masked Interrupt Status

416

0x01C

I2CMICR

WO

0x0000.0000

I2C Master Interrupt Clear

417

0x020

I2CMCR

R/W

0x0000.0000

I2C Master Configuration

418

I2C Slave

 

 

 

 

 

0x000

I2CSOAR

R/W

0x0000.0000

I2C Slave Own Address

420

0x004

I2CSCSR

RO

0x0000.0000

I2C Slave Control/Status

421

0x008

I2CSDR

R/W

0x0000.0000

I2C Slave Data

423

November 16, 2008

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Preliminary

Inter-Integrated Circuit (I2C) Interface

Offset

Name

Type

Reset

Description

See

page

 

 

 

 

 

0x00C

I2CSIMR

R/W

0x0000.0000

I2C Slave Interrupt Mask

424

0x010

I2CSRIS

RO

0x0000.0000

I2C Slave Raw Interrupt Status

425

0x014

I2CSMIS

RO

0x0000.0000

I2C Slave Masked Interrupt Status

426

0x018

I2CSICR

WO

0x0000.0000

I2C Slave Interrupt Clear

427

15.5Register Descriptions (I2C Master)

The remainder of this section lists and describes the I2C master registers, in numerical order by address offset. See also “Register Descriptions (I2C Slave)” on page 419.

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November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 1: I2C Master Slave Address (I2CMSA), offset 0x000

This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which determines if the next operation is a Receive (High), or Send (Low).

I2C Master Slave Address (I2CMSA)

I2C Master 0 base: 0x4002.0000

I2C Master 1 base: 0x4002.1000

Offset 0x000

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

reserved

 

 

 

 

 

 

SA

 

 

 

R/S

Type

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:8

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

7:1

SA

R/W

0

I2C Slave Address

 

 

 

 

This field specifies bits A6 through A0 of the slave address.

0

R/S

R/W

0

Receive/Send

 

 

 

 

The R/S bit specifies if the next operation is a Receive (High) or Send

 

 

 

 

(Low).

 

 

 

 

 

Value

Description

 

 

 

 

0

Send.

1 Receive.

November 16, 2008

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Preliminary

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