LM3S6965 Microcontroller

15.1Block Diagram

Figure 15-1. I2C Block Diagram

15.2Functional Description

EachI2Cmoduleiscomprisedofbothmasterandslavefunctionswhichareimplementedasseparate peripherals. For proper operation, the SDA and SCL pins must be connected to bi-directional open-drain pads. A typical I2C bus configuration is shown in Figure 15-2 on page 393.

See “Inter-Integrated Circuit (I2C) Interface” on page 580 for I2C timing diagrams.

Figure 15-2. I2C Bus Configuration

15.2.1I2C Bus Functional Overview

The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris® microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock line. The bus is considered idle when both lines are High.

Every transaction on the I2C bus is nine bits long, consisting of eight data bits and a single acknowledge bit. The number of bytes per transfer (defined as the time between a valid START and STOP condition, described in “START and STOP Conditions” on page 394) is unrestricted, but each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL.

Preliminary

Inter-Integrated Circuit (I2C) Interface

15.2.1.1 START and STOP Conditions

The protocol of the I2C bus defines two states to begin and end a transaction: START and STOP. A High-to-Low transition on the SDA line while the SCL is High is defined as a START condition, and a Low-to-High transition on the SDA line while SCL is High is defined as a STOP condition. The bus is considered busy after a START condition and free after a STOP condition. See Figure 15-3 on page 394.

Figure 15-3. START and STOP Conditions

15.2.1.2 Data Format with 7-Bit Address

Data transfers follow the format shown in Figure 15-4 on page 394. After the START condition, a slave address is sent. This address is 7-bits long followed by an eighth bit, which is a data direction bit(R/S bitinthe I2CMSA register). Azeroindicatesatransmitoperation(send),andaoneindicates a request for data (receive). A data transfer is always terminated by a STOP condition generated by the master, however, a master can initiate communications with another device on the bus by generating a repeated START condition and addressing another slave without first generating a STOP condition. Various combinations of receive/send formats are then possible within a single transfer.

Figure 15-4. Complete Data Transfer with a 7-Bit Address

The first seven bits of the first byte make up the slave address (see Figure 15-5 on page 394). The eighth bit determines the direction of the message. A zero in the R/S position of the first byte means that the master will write (send) data to the selected slave, and a one in this position means that the master will receive data from the slave.

Figure 15-5. R/S Bit in First Byte

R/S

Slave address

15.2.1.3 Data Validity

The data on the SDA line must be stable during the high period of the clock, and the data line can only change when SCL is Low (see Figure 15-6 on page 395).

Preliminary