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LM3S6965 Microcontroller

Register 9: SSI Interrupt Clear (SSIICR), offset 0x020

The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.

SSI Interrupt Clear (SSIICR)

SSI0 base: 0x4000.8000

Offset 0x020

Type W1C, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

RTIC

RORIC

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

W1C

W1C

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:2

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

1

RTIC

W1C

0

SSI Receive Time-Out Interrupt Clear

 

 

 

 

The RTIC values are defined as follows:

 

 

 

 

Value

Description

 

 

 

 

0

No effect on interrupt.

 

 

 

 

1

Clears interrupt.

0

RORIC

W1C

0

SSI Receive Overrun Interrupt Clear

 

 

 

 

The RORIC values are defined as follows:

 

 

 

 

Value

Description

 

 

 

 

0

No effect on interrupt.

 

 

 

 

1

Clears interrupt.

November 16, 2008

379

Preliminary

Synchronous Serial Interface (SSI)

Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0

The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value.

SSI Peripheral Identification 4 (SSIPeriphID4)

SSI0 base: 0x4000.8000

Offset 0xFD0

Type RO, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

reserved

 

 

 

 

 

 

 

PID4

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:8

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

7:0

PID4

RO

0x00

SSI Peripheral ID Register[7:0]

 

 

 

 

Can be used by software to identify the presence of this peripheral.

380

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4

The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value.

SSI Peripheral Identification 5 (SSIPeriphID5)

SSI0 base: 0x4000.8000

Offset 0xFD4

Type RO, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

reserved

 

 

 

 

 

 

 

PID5

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:8

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

7:0

PID5

RO

0x00

SSI Peripheral ID Register[15:8]

 

 

 

 

Can be used by software to identify the presence of this peripheral.

November 16, 2008

381

Preliminary

Synchronous Serial Interface (SSI)

Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8

The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value.

SSI Peripheral Identification 6 (SSIPeriphID6)

SSI0 base: 0x4000.8000

Offset 0xFD8

Type RO, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

reserved

 

 

 

 

 

 

 

PID6

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:8

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

7:0

PID6

RO

0x00

SSI Peripheral ID Register[23:16]

 

 

 

 

Can be used by software to identify the presence of this peripheral.

382

November 16, 2008

Preliminary

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