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LM3S6965 Microcontroller

Register 6: SSI Interrupt Mask (SSIIM), offset 0x014

The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits are cleared to 0 on reset.

On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to theparticularbitsetsthemask,enablingtheinterrupttoberead. Awriteof0clearsthecorresponding mask.

SSI Interrupt Mask (SSIIM)

SSI0 base: 0x4000.8000

Offset 0x014

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

reserved

 

 

 

 

 

TXIM

RXIM

RTIM

RORIM

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:4

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

3

TXIM

R/W

0

SSI Transmit FIFO Interrupt Mask

 

 

 

 

The TXIM values are defined as follows:

 

 

 

 

Value

Description

 

 

 

 

0

TX FIFO half-full or less condition interrupt is masked.

 

 

 

 

1

TX FIFO half-full or less condition interrupt is not masked.

2

RXIM

R/W

0

SSI Receive FIFO Interrupt Mask

 

 

 

 

The RXIM values are defined as follows:

 

 

 

 

Value

Description

 

 

 

 

0

RX FIFO half-full or more condition interrupt is masked.

 

 

 

 

1

RX FIFO half-full or more condition interrupt is not masked.

1

RTIM

R/W

0

SSI Receive Time-Out Interrupt Mask

 

 

 

 

The RTIM values are defined as follows:

 

 

 

 

Value

Description

 

 

 

 

0

RX FIFO time-out interrupt is masked.

 

 

 

 

1

RX FIFO time-out interrupt is not masked.

November 16, 2008

375

Preliminary

Synchronous Serial Interface (SSI)

Bit/Field

Name

Type

Reset

Description

0

RORIM

R/W

0

SSI Receive Overrun Interrupt Mask

 

 

 

 

The RORIM values are defined as follows:

 

 

 

 

Value

Description

 

 

 

 

0

RX FIFO overrun interrupt is masked.

 

 

 

 

1

RX FIFO overrun interrupt is not masked.

376

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018

The SSIRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect.

SSI Raw Interrupt Status (SSIRIS)

SSI0 base: 0x4000.8000

Offset 0x018

Type RO, reset 0x0000.0008

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

reserved

 

 

 

 

 

TXRIS

RXRIS

RTRIS

RORRIS

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

Bit/Field

Name

Type

Reset

Description

31:4

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

3

TXRIS

RO

1

SSI Transmit FIFO Raw Interrupt Status

 

 

 

 

Indicates that the transmit FIFO is half full or less, when set.

2

RXRIS

RO

0

SSI Receive FIFO Raw Interrupt Status

 

 

 

 

Indicates that the receive FIFO is half full or more, when set.

1

RTRIS

RO

0

SSI Receive Time-Out Raw Interrupt Status

 

 

 

 

Indicates that the receive time-out has occurred, when set.

0

RORRIS

RO

0

SSI Receive Overrun Raw Interrupt Status

 

 

 

 

Indicates that the receive FIFO has overflowed, when set.

November 16, 2008

377

Preliminary

Synchronous Serial Interface (SSI)

Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C

The SSIMIS registeristhemaskedinterruptstatusregister. Onaread,thisregistergivesthecurrent masked status value of the corresponding interrupt. A write has no effect.

SSI Masked Interrupt Status (SSIMIS)

SSI0 base: 0x4000.8000

Offset 0x01C

Type RO, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

reserved

 

 

 

 

 

TXMIS

RXMIS

RTMIS

RORMIS

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:4

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

3

TXMIS

RO

0

SSI Transmit FIFO Masked Interrupt Status

 

 

 

 

Indicates that the transmit FIFO is half full or less, when set.

2

RXMIS

RO

0

SSI Receive FIFO Masked Interrupt Status

 

 

 

 

Indicates that the receive FIFO is half full or more, when set.

1

RTMIS

RO

0

SSI Receive Time-Out Masked Interrupt Status

 

 

 

 

Indicates that the receive time-out has occurred, when set.

0

RORMIS

RO

0

SSI Receive Overrun Masked Interrupt Status

 

 

 

 

Indicates that the receive FIFO has overflowed, when set.

378

November 16, 2008

Preliminary

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