Synchronous Serial Interface (SSI)

Figure 14-11. MICROWIRE Frame Format (Continuous Transfer)

SSIClk

In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk.

Figure 14-12 on page 364 illustrates these setup and hold time requirements. With respect to the SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss must have a setup of at least two times the period of SSIClk on which the SSI operates. With respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one SSIClk period.

Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements

tSetup=(2*tSSIClk)

tHold=tSSIClk

SSIClk

SSIFss

SSIRx

First RX data to be sampled by SSI slave

14.3Initialization and Configuration

To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register. For each of the frame formats, the SSI is configured using the following steps:

1.Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration changes.

2.Select whether the SSI is a master or slave:

a.For master operations, set the SSICR1 register to 0x0000.0000.

b.For slave mode (output enabled), set the SSICR1 register to 0x0000.0004.

c.For slave mode (output disabled), set the SSICR1 register to 0x0000.000C.

3.Configure the clock prescale divisor by writing the SSICPSR register.

4.Write the SSICR0 register with the following configuration:

Preliminary

LM3S6965 Microcontroller

■Serial clock rate (SCR)

■Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO)

■The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF)

■The data size (DSS)

5.Enable the SSI by setting the SSE bit in the SSICR1 register.

As an example, assume the SSI must be configured to operate with the following parameters:

■Master operation

■Freescale SPI mode (SPO=1, SPH=1)

■1 Mbps bit rate

■8 data bits

Assuming the system clock is 20 MHz, the bit rate calculation would be:

FSSIClk = FSysClk / (CPSDVSR * (1 + SCR))

1x106 = 20x106 / (CPSDVSR * (1 + SCR))

In this case, if CPSDVSR=2, SCR must be 9.

The configuration sequence would be as follows:

1.Ensure that the SSE bit in the SSICR1 register is disabled.

2.Write the SSICR1 register with a value of 0x0000.0000.

3.Write the SSICPSR register with a value of 0x0000.0002.

4.Write the SSICR0 register with a value of 0x0000.09C7.

5.The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1.

14.4Register Map

Table 14-1 on page 365 lists the SSI registers. The offset listed is a hexadecimal increment to the register’s address, relative to that SSI module’s base address:

■ SSI0: 0x4000.8000

Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control registers are reprogrammed.

Table 14-1. SSI Register Map

Preliminary