Synchronous Serial Interface (SSI)

Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer)

SSIClk

SSIFss

4 to 16 bits

In this mode, SSIClk and SSIFss are forced Low, and the transmit data line SSITx is tristated whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is pulsedHighforone SSIClk period. Thevaluetobetransmittedisalsotransferredfromthetransmit FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIClk, the MSB of the 4 to 16-bit data frame is shifted out on the SSITx pin. Likewise, the MSB of the received data is shifted onto the SSIRx pin by the off-chip serial slave device.

Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on thefallingedgeofeach SSIClk. Thereceiveddataistransferredfromtheserialshiftertothereceive FIFO on the first rising edge of SSIClk after the LSB has been latched.

Figure 14-3 on page 358 shows the Texas Instruments synchronous serial frame format when back-to-back frames are transmitted.

Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer)

14.2.4.2 Freescale SPI Frame Format

The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave select. The main feature of the Freescale SPI format is that the inactive state and phase of the SSIClk signalareprogrammablethroughthe SPO and SPH bitswithinthe SSISCR0 controlregister.

SPO Clock Polarity Bit

When the SPO clock polarity control bit is Low, it produces a steady state Low value on the SSIClk pin. If the SPO bit is High, a steady state High value is placed on the SSIClk pin when data is not being transferred.

Preliminary