Synchronous Serial Interface (SSI)

internalFIFOmemoriesallowinguptoeight16-bitvaluestobestoredindependentlyinbothtransmit and receive modes.

14.2.1Bit Rate Generation

The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by peripheral devices.

The serial bit rate is derived by dividing down the input clock (FSysClk). The clock is first divided byanevenprescalevalue CPSDVSR from2to254,whichisprogrammedinthe SSI Clock Prescale (SSICPSR) register (see page 374). The clock is further divided by a value from 1 to 256, which is 1+ SCR,where SCR isthevalueprogrammedinthe SSI Control0 (SSICR0) register(seepage367).

The frequency of the output clock SSIClk is defined by:

SSIClk = FSysClk / (CPSDVSR * (1 + SCR))

Note: Although the SSIClk transmit clock can theoretically be 25 MHz, the module may not be abletooperateatthatspeed. Formastermode,thesystemclockmustbeatleasttwotimes faster than the SSIClk. For slave mode, the system clock must be at least 12 times faster than the SSIClk.

See “Synchronous Serial Interface (SSI)” on page 578 to view SSI timing parameters.

14.2.2FIFO Operation

14.2.2.1 Transmit FIFO

The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 371), and data is stored in the FIFO until it is read out by the transmission logic.

When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial conversion and transmission to the attached slave or master, respectively, through the SSITx pin.

14.2.2.2 Receive FIFO

The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. Received data from the serial interface is stored in the buffer until read out by the CPU, which accesses the read FIFO by reading the SSIDR register.

When configured as a master or slave, serial data received through the SSIRx pin is registered prior to parallel loading into the attached slave or master receive FIFO, respectively.

14.2.3Interrupts

The SSI can generate interrupts when the following conditions are observed:

■Transmit FIFO service

■Receive FIFO service

■Receive FIFO time-out

■Receive FIFO overrun

Preliminary