LM3S6965 Microcontroller
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C
The UARTRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt. A write has no effect.
UART Raw Interrupt Status (UARTRIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x03C
Type RO, reset 0x0000.000F
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31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
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reserved |
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Type |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
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15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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reserved |
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OERIS |
BERIS |
PERIS |
FERIS |
RTRIS |
TXRIS |
RXRIS |
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reserved |
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Type |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
Bit/Field |
Name |
Type |
Reset |
Description |
31:11 |
reserved |
RO |
0x00 |
Software should not rely on the value of a reserved bit. To provide |
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|
compatibility with future products, the value of a reserved bit should be |
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preserved across a read-modify-write operation. |
10 |
OERIS |
RO |
0 |
UART Overrun Error Raw Interrupt Status |
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Gives the raw interrupt state (prior to masking) of this interrupt. |
9 |
BERIS |
RO |
0 |
UART Break Error Raw Interrupt Status |
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Gives the raw interrupt state (prior to masking) of this interrupt. |
8 |
PERIS |
RO |
0 |
UART Parity Error Raw Interrupt Status |
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Gives the raw interrupt state (prior to masking) of this interrupt. |
7 |
FERIS |
RO |
0 |
UART Framing Error Raw Interrupt Status |
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Gives the raw interrupt state (prior to masking) of this interrupt. |
6 |
RTRIS |
RO |
0 |
UART Receive Time-Out Raw Interrupt Status |
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Gives the raw interrupt state (prior to masking) of this interrupt. |
5 |
TXRIS |
RO |
0 |
UART Transmit Raw Interrupt Status |
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Gives the raw interrupt state (prior to masking) of this interrupt. |
4 |
RXRIS |
RO |
0 |
UART Receive Raw Interrupt Status |
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Gives the raw interrupt state (prior to masking) of this interrupt. |
3:0 |
reserved |
RO |
0xF |
Software should not rely on the value of a reserved bit. To provide |
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|
|
compatibility with future products, the value of a reserved bit should be |
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|
|
|
preserved across a read-modify-write operation. |
November 16, 2008 |
339 |
Preliminary
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040
The UARTMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect.
UART Masked Interrupt Status (UARTMIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x040
Type RO, reset 0x0000.0000
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31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
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reserved |
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Type |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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reserved |
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|
OEMIS |
BEMIS |
PEMIS |
FEMIS |
RTMIS |
TXMIS |
RXMIS |
|
reserved |
|
|
Type |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Bit/Field |
Name |
Type |
Reset |
Description |
31:11 |
reserved |
RO |
0x00 |
Software should not rely on the value of a reserved bit. To provide |
|
|
|
|
compatibility with future products, the value of a reserved bit should be |
|
|
|
|
preserved across a read-modify-write operation. |
10 |
OEMIS |
RO |
0 |
UART Overrun Error Masked Interrupt Status |
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|
|
|
Gives the masked interrupt state of this interrupt. |
9 |
BEMIS |
RO |
0 |
UART Break Error Masked Interrupt Status |
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|
|
Gives the masked interrupt state of this interrupt. |
8 |
PEMIS |
RO |
0 |
UART Parity Error Masked Interrupt Status |
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|
Gives the masked interrupt state of this interrupt. |
7 |
FEMIS |
RO |
0 |
UART Framing Error Masked Interrupt Status |
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|
Gives the masked interrupt state of this interrupt. |
6 |
RTMIS |
RO |
0 |
UART Receive Time-Out Masked Interrupt Status |
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|
|
Gives the masked interrupt state of this interrupt. |
5 |
TXMIS |
RO |
0 |
UART Transmit Masked Interrupt Status |
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|
Gives the masked interrupt state of this interrupt. |
4 |
RXMIS |
RO |
0 |
UART Receive Masked Interrupt Status |
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|
Gives the masked interrupt state of this interrupt. |
3:0 |
reserved |
RO |
0 |
Software should not rely on the value of a reserved bit. To provide |
|
|
|
|
compatibility with future products, the value of a reserved bit should be |
|
|
|
|
preserved across a read-modify-write operation. |
340 |
November 16, 2008 |
Preliminary
LM3S6965 Microcontroller
Register 13: UART Interrupt Clear (UARTICR), offset 0x044
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
UART Interrupt Clear (UARTICR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x044
Type W1C, reset 0x0000.0000
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31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
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reserved |
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Type |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
RO |
Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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reserved |
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OEIC |
BEIC |
PEIC |
FEIC |
RTIC |
TXIC |
RXIC |
|
reserved |
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|
Type |
RO |
RO |
RO |
RO |
RO |
W1C |
W1C |
W1C |
W1C |
W1C |
W1C |
W1C |
RO |
RO |
RO |
RO |
Reset |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
Bit/Field |
Name |
Type |
Reset |
Description |
31:11 |
reserved |
RO |
0x00 |
Software should not rely on the value of a reserved bit. To provide |
|
|
|
|
compatibility with future products, the value of a reserved bit should be |
|
|
|
|
preserved across a read-modify-write operation. |
10 |
OEIC |
W1C |
0 |
Overrun Error Interrupt Clear |
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|
|
The OEIC values are defined as follows: |
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|
Value Description |
0 No effect on the interrupt.
1 Clears interrupt.
9 |
BEIC |
W1C |
0 |
Break Error Interrupt Clear |
The BEIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
8 |
PEIC |
W1C |
0 |
Parity Error Interrupt Clear |
The PEIC values are defined as follows:
Value Description
0 No effect on the interrupt.
1 Clears interrupt.
November 16, 2008 |
341 |
Preliminary
Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field |
Name |
Type |
Reset |
Description |
|
7 |
FEIC |
W1C |
0 |
Framing Error Interrupt Clear |
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The FEIC values are defined as follows: |
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|
Value |
Description |
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|
|
|
0 |
No effect on the interrupt. |
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|
|
1 |
Clears interrupt. |
6 |
RTIC |
W1C |
0 |
Receive Time-Out Interrupt Clear |
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The RTIC values are defined as follows: |
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Value |
Description |
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0 |
No effect on the interrupt. |
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|
1 |
Clears interrupt. |
5 |
TXIC |
W1C |
0 |
Transmit Interrupt Clear |
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The TXIC values are defined as follows: |
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|
Value |
Description |
|
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|
|
0 |
No effect on the interrupt. |
|
|
|
|
1 |
Clears interrupt. |
4 |
RXIC |
W1C |
0 |
Receive Interrupt Clear |
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The RXIC values are defined as follows: |
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|
Value |
Description |
|
|
|
|
0 |
No effect on the interrupt. |
|
|
|
|
1 |
Clears interrupt. |
3:0 |
reserved |
RO |
0x00 |
Software should not rely on the value of a reserved bit. To provide |
|
|
|
|
|
compatibility with future products, the value of a reserved bit should be |
|
|
|
|
|
preserved across a read-modify-write operation. |
|
342 |
November 16, 2008 |
Preliminary