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Universal Asynchronous Receivers/Transmitters (UARTs)

Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028

The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared on reset. When changing the UARTFBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 316 for configuration details.

UART Fractional Baud-Rate Divisor (UARTFBRD)

UART0 base: 0x4000.C000

UART1 base: 0x4000.D000

UART2 base: 0x4000.E000

Offset 0x028

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

reserved

 

 

 

 

 

 

DIVFRAC

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:6

reserved

RO

0x00

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

5:0

DIVFRAC

R/W

0x000

Fractional Baud-Rate Divisor

330

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 7: UART Line Control (UARTLCRH), offset 0x02C

The UARTLCRH register is the line control register. Serial parameters such as data length, parity, and stop bit selection are implemented in this register.

When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH register.

UART Line Control (UARTLCRH)

UART0 base: 0x4000.C000

UART1 base: 0x4000.D000

UART2 base: 0x4000.E000

Offset 0x02C

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

reserved

 

 

 

SPS

WLEN

 

FEN

STP2

EPS

PEN

BRK

Type

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:8

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

7

SPS

R/W

0

UART Stick Parity Select

 

 

 

 

Whenbits1,2,and7of UARTLCRH areset,theparitybitistransmitted

 

 

 

 

and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the

 

 

 

 

parity bit is transmitted and checked as a 1.

 

 

 

 

When this bit is cleared, stick parity is disabled.

6:5

WLEN

R/W

0

UART Word Length

 

 

 

 

The bits indicate the number of data bits transmitted or received in a

 

 

 

 

frame as follows:

 

 

 

 

Value

Description

 

 

 

 

0x3

8 bits

 

 

 

 

0x2

7 bits

 

 

 

 

0x1

6 bits

 

 

 

 

0x0

5 bits (default)

4

FEN

R/W

0

UART Enable FIFOs

 

 

 

 

Ifthisbitissetto1,transmitandreceiveFIFObuffersareenabled(FIFO

 

 

 

 

mode).

 

When cleared to 0, FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers.

November 16, 2008

331

Preliminary

Universal Asynchronous Receivers/Transmitters (UARTs)

Bit/Field

Name

Type

Reset

Description

3

STP2

R/W

0

UART Two Stop Bits Select

 

 

 

 

If this bit is set to 1, two stop bits are transmitted at the end of a frame.

 

 

 

 

The receive logic does not check for two stop bits being received.

2

EPS

R/W

0

UART Even Parity Select

 

 

 

 

If this bit is set to 1, even parity generation and checking is performed

 

 

 

 

during transmission and reception, which checks for an even number

 

 

 

 

of 1s in data and parity bits.

 

 

 

 

When cleared to 0, then odd parity is performed, which checks for an

 

 

 

 

odd number of 1s.

 

 

 

 

This bit has no effect when parity is disabled by the PEN bit.

1

PEN

R/W

0

UART Parity Enable

 

 

 

 

Ifthisbitissetto1,paritycheckingandgenerationisenabled;otherwise,

 

 

 

 

parity is disabled and no parity bit is added to the data frame.

0

BRK

R/W

0

UART Send Break

 

 

 

 

Ifthisbitissetto1,aLowleveliscontinuallyoutputonthe UnTX output,

after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two frames (character periods). For normal use, this bit must be cleared to 0.

332

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 8: UART Control (UARTCTL), offset 0x030

The UARTCTL register is the control register. All the bits are cleared on reset except for the

Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1.

To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration changeinthemodule,the UARTEN bitmustbeclearedbeforetheconfigurationchangesarewritten. If the UART is disabled during a transmit or receive operation, the current transaction is completed prior to the UART stopping.

Note: The UARTCTL registershouldnotbechangedwhiletheUARTisenabledorelsetheresults are unpredictable. The following sequence is recommended for making changes to the UARTCTL register.

1.Disable the UART.

2.Wait for the end of transmission or reception of the current character.

3.FlushthetransmitFIFObydisablingbit4(FEN)inthelinecontrolregister(UARTLCRH).

4.Reprogram the control register.

5.Enable the UART.

UART Control (UARTCTL)

UART0 base: 0x4000.C000

UART1 base: 0x4000.D000

UART2 base: 0x4000.E000

Offset 0x030

Type R/W, reset 0x0000.0300

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

reserved

 

 

RXE

TXE

LBE

 

reserved

 

SIRLP

SIREN

UARTEN

Type

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

RO

RO

RO

RO

R/W

R/W

R/W

Reset

0

0

0

0

0

0

1

1

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:10

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

9

RXE

R/W

1

UART Receive Enable

 

 

 

 

If this bit is set to 1, the receive section of the UART is enabled. When

 

 

 

 

theUARTisdisabledinthemiddleofareceive,itcompletesthecurrent

 

 

 

 

character before stopping.

 

 

 

 

Note:

To enable reception, the UARTEN bit must also be set.

November 16, 2008

333

Preliminary

Universal Asynchronous Receivers/Transmitters (UARTs)

Bit/Field

Name

Type

Reset

8

TXE

R/W

1

7

LBE

R/W

0

6:3

reserved

RO

0

Description

UART Transmit Enable

If this bit is set to 1, the transmit section of the UART is enabled. When the UART is disabled in the middle of a transmission, it completes the current character before stopping.

Note: To enable transmission, the UARTEN bit must also be set.

UART Loop Back Enable

If this bit is set to 1, the UnTX path is fed through the UnRX path.

Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.

2

SIRLP

R/W

0

UART SIR Low Power Mode

This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active High pulse with a width of 3/16thofthebitperiod. Ifthisbitissetto1,low-levelbitsaretransmitted with a pulse width which is 3 times the period of the IrLPBaud16 input signal,regardlessoftheselectedbitrate. Settingthisbituseslesspower, but might reduce transmission distances. See page 328 for more information.

1

SIREN

R/W

0

UART SIR Enable

If this bit is set to 1, the IrDA SIR block is enabled, and the UART will transmit and receive data using SIR protocol.

0

UARTEN

R/W

0

UART Enable

If this bit is set to 1, the UART is enabled. When the UART is disabled in the middle of transmission or reception, it completes the current character before stopping.

334

November 16, 2008

Preliminary

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