Добавил:
Опубликованный материал нарушает ваши авторские права? Сообщите нам.
Вуз: Предмет: Файл:
БЭМЗ полищук доки / Склад / Datasheet_LM3S6965.pdf
Скачиваний:
10
Добавлен:
21.12.2020
Размер:
6.13 Mб
Скачать

Universal Asynchronous Receivers/Transmitters (UARTs)

Register 3: UART Flag (UARTFR), offset 0x018

The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and TXFE and RXFE bits are 1.

UART Flag (UARTFR)

UART0 base: 0x4000.C000

UART1 base: 0x4000.D000

UART2 base: 0x4000.E000

Offset 0x018

Type RO, reset 0x0000.0090

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

reserved

 

 

 

TXFE

RXFF

TXFF

RXFE

BUSY

 

reserved

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

1

0

0

1

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:8

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

7

TXFE

RO

1

UART Transmit FIFO Empty

 

 

 

 

The meaning of this bit depends on the state of the FEN bit in the

 

 

 

 

UARTLCRH register.

 

 

 

 

IftheFIFOisdisabled(FEN is0),thisbitissetwhenthetransmitholding

 

 

 

 

register is empty.

 

 

 

 

If the FIFO is enabled (FEN is 1), this bit is set when the transmit FIFO

 

 

 

 

is empty.

6

RXFF

RO

0

UART Receive FIFO Full

 

 

 

 

The meaning of this bit depends on the state of the FEN bit in the

 

 

 

 

UARTLCRH register.

 

 

 

 

If the FIFO is disabled, this bit is set when the receive holding register

 

 

 

 

is full.

 

 

 

 

If the FIFO is enabled, this bit is set when the receive FIFO is full.

5

TXFF

RO

0

UART Transmit FIFO Full

 

 

 

 

The meaning of this bit depends on the state of the FEN bit in the

 

 

 

 

UARTLCRH register.

If the FIFO is disabled, this bit is set when the transmit holding register is full.

If the FIFO is enabled, this bit is set when the transmit FIFO is full.

326

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Bit/Field

Name

Type

Reset

Description

4

RXFE

RO

1

UART Receive FIFO Empty

 

 

 

 

The meaning of this bit depends on the state of the FEN bit in the

 

 

 

 

UARTLCRH register.

 

 

 

 

If the FIFO is disabled, this bit is set when the receive holding register

 

 

 

 

is empty.

 

 

 

 

If the FIFO is enabled, this bit is set when the receive FIFO is empty.

3

BUSY

RO

0

UART Busy

 

 

 

 

When this bit is 1, the UART is busy transmitting data. This bit remains

 

 

 

 

set until the complete byte, including all stop bits, has been sent from

 

 

 

 

the shift register.

 

 

 

 

This bit is set as soon as the transmit FIFO becomes non-empty

 

 

 

 

(regardless of whether UART is enabled).

2:0

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

November 16, 2008

327

Preliminary

Universal Asynchronous Receivers/Transmitters (UARTs)

Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020

The UARTILPR register is an 8-bit read/write register that stores the low-power counter divisor valueusedtoderivethelow-powerSIRpulsewidthclockbydividingdownthesystemclock(SysClk). All the bits are cleared to 0 when reset.

The internal IrLPBaud16 clock is generated by dividing down SysClk according to the low-power divisor value written to UARTILPR. The duration of SIR pulses generated when low-power mode is enabled is three times the period of the IrLPBaud16 clock. The low-power divisor value is calculated as follows:

ILPDVSR = SysClk / FIrLPBaud16

where FIrLPBaud16 is nominally 1.8432 MHz.

Youmustchoosethedivisorsothat1.42MHz< FIrLPBaud16 <2.12MHz,whichresultsinalow-power pulse duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum frequency of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but that pulses greater than 1.4 μs are accepted as valid pulses.

Note: Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being generated.

UART IrDA Low-Power Register (UARTILPR)

UART0 base: 0x4000.C000

UART1 base: 0x4000.D000

UART2 base: 0x4000.E000

Offset 0x020

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

reserved

 

 

 

 

 

 

ILPDVSR

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:8

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

7:0

ILPDVSR

R/W

0x00

IrDA Low-Power Divisor

 

 

 

 

This is an 8-bit low-power divisor value.

328

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024

The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared onreset.Theminimumpossibledivideratiois1(whenUARTIBRD=0),inwhichcasetheUARTFBRD registerisignored. Whenchangingthe UARTIBRD register,thenewvaluedoesnottakeeffectuntil transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 316 for configuration details.

UART Integer Baud-Rate Divisor (UARTIBRD)

UART0 base: 0x4000.C000

UART1 base: 0x4000.D000

UART2 base: 0x4000.E000

Offset 0x024

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

DIVINT

 

 

 

 

 

 

 

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:16

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

15:0

DIVINT

R/W

0x0000

Integer Baud-Rate Divisor

November 16, 2008

329

Preliminary

Соседние файлы в папке Склад