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LM3S6965 Microcontroller

Offset

Name

Type

Reset

Description

See

page

 

 

 

 

 

0x024

UARTIBRD

R/W

0x0000.0000

UART Integer Baud-Rate Divisor

329

0x028

UARTFBRD

R/W

0x0000.0000

UART Fractional Baud-Rate Divisor

330

0x02C

UARTLCRH

R/W

0x0000.0000

UART Line Control

331

0x030

UARTCTL

R/W

0x0000.0300

UART Control

333

0x034

UARTIFLS

R/W

0x0000.0012

UART Interrupt FIFO Level Select

335

0x038

UARTIM

R/W

0x0000.0000

UART Interrupt Mask

337

0x03C

UARTRIS

RO

0x0000.000F

UART Raw Interrupt Status

339

0x040

UARTMIS

RO

0x0000.0000

UART Masked Interrupt Status

340

0x044

UARTICR

W1C

0x0000.0000

UART Interrupt Clear

341

0xFD0

UARTPeriphID4

RO

0x0000.0000

UART Peripheral Identification 4

343

0xFD4

UARTPeriphID5

RO

0x0000.0000

UART Peripheral Identification 5

344

0xFD8

UARTPeriphID6

RO

0x0000.0000

UART Peripheral Identification 6

345

0xFDC

UARTPeriphID7

RO

0x0000.0000

UART Peripheral Identification 7

346

0xFE0

UARTPeriphID0

RO

0x0000.0011

UART Peripheral Identification 0

347

0xFE4

UARTPeriphID1

RO

0x0000.0000

UART Peripheral Identification 1

348

0xFE8

UARTPeriphID2

RO

0x0000.0018

UART Peripheral Identification 2

349

0xFEC

UARTPeriphID3

RO

0x0000.0001

UART Peripheral Identification 3

350

0xFF0

UARTPCellID0

RO

0x0000.000D

UART PrimeCell Identification 0

351

0xFF4

UARTPCellID1

RO

0x0000.00F0

UART PrimeCell Identification 1

352

0xFF8

UARTPCellID2

RO

0x0000.0005

UART PrimeCell Identification 2

353

0xFFC

UARTPCellID3

RO

0x0000.00B1

UART PrimeCell Identification 3

354

13.5Register Descriptions

The remainder of this section lists and describes the UART registers, in numerical order by address offset.

November 16, 2008

321

Preliminary

Universal Asynchronous Receivers/Transmitters (UARTs)

Register 1: UART Data (UARTDR), offset 0x000

This register is the data register (the interface to the FIFOs).

When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs aredisabled,dataisstoredinthetransmitterholdingregister(thebottomwordofthetransmitFIFO). A write to this register initiates a transmission from the UART.

For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO. If FIFOs are disabled, the data byte and statusarestoredinthereceivingholdingregister(thebottomwordofthereceiveFIFO). Thereceived data can be retrieved by reading this register.

UART Data (UARTDR)

UART0 base: 0x4000.C000

UART1 base: 0x4000.D000

UART2 base: 0x4000.E000

Offset 0x000

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

reserved

 

OE

BE

PE

FE

 

 

 

 

DATA

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:12

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

11

OE

RO

0

UART Overrun Error

 

 

 

 

The OE values are defined as follows:

 

 

 

 

Value Description

 

 

 

 

0 There has been no data loss due to a FIFO overrun.

 

 

 

 

1 New data was received when the FIFO was full, resulting in

 

 

 

 

data loss.

10

BE

RO

0

UART Break Error

 

 

 

 

This bit is set to 1 when a break condition is detected, indicating that

 

 

 

 

the receive data input was held Low for longer than a full-word

 

 

 

 

transmission time (defined as start, data, parity, and stop bits).

In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the received data input goes to a 1 (marking state) and the next valid start bit is received.

322

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Bit/Field

Name

Type

Reset

Description

9

PE

RO

0

UART Parity Error

 

 

 

 

This bit is set to 1 when the parity of the received data character does

 

 

 

 

not match the parity defined by bits 2 and 7 of the UARTLCRH register.

 

 

 

 

In FIFO mode, this error is associated with the character at the top of

 

 

 

 

the FIFO.

8

FE

RO

0

UART Framing Error

 

 

 

 

This bit is set to 1 when the received character does not have a valid

 

 

 

 

stop bit (a valid stop bit is 1).

7:0

DATA

R/W

0

Data Transmitted or Received

 

 

 

 

When written, the data that is to be transmitted via the UART. When

 

 

 

 

read, the data that was received by the UART.

November 16, 2008

323

Preliminary

Universal Asynchronous Receivers/Transmitters (UARTs)

Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004

The UARTRSR/UARTECR register is the receive status register/error clear register.

In addition to the UARTDR register, receive status can also be read from the UARTRSR register. If the status is read from this register, then the status information corresponds to the entry read from UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when an overrun condition occurs.

The UARTRSR register cannot be written.

A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors. All the bits are cleared to 0 on reset.

Reads

UART Receive Status/Error Clear (UARTRSR/UARTECR)

UART0 base: 0x4000.C000

UART1 base: 0x4000.D000

UART2 base: 0x4000.E000

Offset 0x004

Type RO, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

reserved

 

 

 

 

 

OE

BE

PE

FE

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:4

reserved

RO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

3

OE

RO

0

UART Overrun Error

 

 

 

 

When this bit is set to 1, data is received and the FIFO is already full.

 

 

 

 

This bit is cleared to 0 by a write to UARTECR.

 

 

 

 

The FIFO contents remain valid since no further data is written when

 

 

 

 

the FIFO is full, only the contents of the shift register are overwritten.

 

 

 

 

The CPU must now read the data in order to empty the FIFO.

2

BE

RO

0

UART Break Error

This bit is set to 1 when a break condition is detected, indicating that the received data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits).

This bit is cleared to 0 by a write to UARTECR.

In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.

324

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Bit/Field

Name

Type

Reset

Description

1

PE

RO

0

UART Parity Error

 

 

 

 

This bit is set to 1 when the parity of the received data character does

 

 

 

 

not match the parity defined by bits 2 and 7 of the UARTLCRH register.

 

 

 

 

This bit is cleared to 0 by a write to UARTECR.

0

FE

RO

0

UART Framing Error

This bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1).

This bit is cleared to 0 by a write to UARTECR.

In FIFO mode, this error is associated with the character at the top of the FIFO.

Writes

UART Receive Status/Error Clear (UARTRSR/UARTECR)

UART0 base: 0x4000.C000

UART1 base: 0x4000.D000

UART2 base: 0x4000.E000

Offset 0x004

Type WO, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

reserved

 

 

 

 

 

 

 

DATA

 

 

 

Type

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

WO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:8

reserved

WO

0

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

7:0

DATA

WO

0

Error Clear

 

 

 

 

A write to this register of any data clears the framing, parity, break, and

 

 

 

 

overrun flags.

November 16, 2008

325

Preliminary

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