LM3S6965 Microcontroller

■Break Error

■Parity Error

■Framing Error

■Receive Timeout

■Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met)

■Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met)

All of the interrupt events are ORed together before being sent to the interrupt controller, so the UART can only generate a single interrupt request to the controller at any given time. Software can service multiple interrupt events in a single interrupt service routine by reading the UART Masked Interrupt Status (UARTMIS) register (see page 340).

The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt Mask (UARTIM ) register (see page 337) by setting the corresponding IM bit to 1. If interrupts are not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS) register (see page 339).

Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 341).

The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data is received over a 32-bit period. The receive timeout interrupt is cleared either when the FIFO becomes empty through reading all the data (or by reading the holding register), or when a 1 is written to the corresponding bit in the UARTICR register.

13.2.7Loopback Operation

The UART can be placed into an internal loopback mode for diagnostic or debug work. This is accomplished by setting the LBE bit in the UARTCTL register (see page 333). In loopback mode, data transmitted on UnTx is received on the UnRx input.

13.2.8IrDA SIR block

The IrDA SIR block contains an IrDA serial IR (SIR) protocol encoder/decoder. When enabled, the SIR block uses the UnTx and UnRx pins for the SIR protocol, which should be connected to an IR transceiver.

The SIR block can receive and transmit, but it is only half-duplex so it cannot do both at the same time. Transmission must be stopped before data can be received. The IrDA SIR physical layer specifies a minimum 10-ms delay between transmission and reception.

13.3Initialization and Configuration

To use the UARTs, the peripheral clock must be enabled by setting the UART0, UART1, or UART2 bits in the RCGC1 register.

This section discusses the steps that are required to use a UART module. For this example, the UART clock is assumed to be 20 MHz and the desired UART configuration is:

■115200 baud rate

■Data length of 8 bits

Preliminary

Universal Asynchronous Receivers/Transmitters (UARTs)

■One stop bit

■No parity

■FIFOs disabled

■No interrupts

The first thing to consider when programming the UART is the baud-rate divisor (BRD), since the UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the equation described in “Baud-Rate Generation” on page 316, the BRD can be calculated:

BRD = 20,000,000 / (16 * 115,200) = 10.8507

which means that the DIVINT field of the UARTIBRD register (see page 329) should be set to 10. The value to be loaded into the UARTFBRD register (see page 330) is calculated by the equation:

UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54

With the BRD values in hand, the UART configuration is written to the module in the following order:

1.Disable the UART by clearing the UARTEN bit in the UARTCTL register.

2.Write the integer portion of the BRD to the UARTIBRD register.

3.Write the fractional portion of the BRD to the UARTFBRD register.

4.Write the desired serial parameters to the UARTLCRH register (in this case, a value of 0x0000.0060).

5.Enable the UART by setting the UARTEN bit in the UARTCTL register.

13.4Register Map

Table 13-1 on page 320 lists the UART registers. The offset listed is a hexadecimal increment to the register’s address, relative to that UART’s base address:

■UART0: 0x4000.C000

■UART1: 0x4000.D000

■UART2: 0x4000.E000

Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 333) before any of the control registers are reprogrammed. When the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping.

Table 13-1. UART Register Map

Preliminary