LM3S6965 Microcontroller

13.1Block Diagram

13.2Functional Description

Each Stellaris® UART performs the functions of parallel-to-serial and serial-to-parallel conversions. It is similar in functionality to a 16C550 UART, but is not register compatible.

The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control (UARTCTL) register(seepage333). Transmitandreceivearebothenabledoutofreset. Beforeany control registers are programmed, the UART must be disabled by clearing the UARTEN bit in UARTCTL. IftheUARTisdisabledduringaTXorRXoperation,thecurrenttransactioniscompleted prior to the UART stopping.

The UART peripheral also includes a serial IR (SIR) encoder/decoder block that can be connected to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed using the UARTCTL register.

13.2.1Transmit/Receive Logic

The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. The control logic outputs the serial bit stream beginning with a start bit, and followed by the data

Preliminary

Universal Asynchronous Receivers/Transmitters (UARTs)

bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control registers. See Figure 13-2 on page 316 for details.

The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also performed, and their status accompanies the data that is written to the receive FIFO.

Figure 13-2. UART Character Frame

05-8 data bits

nParity bit

13.2.2Baud-Rate Generation

The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The number formed by these two values is used by the baud-rate generator to determine the bit period. Having a fractional baud-rate divider allows the UART to generate all the standard baud rates.

The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register (see page 329) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor (UARTFBRD) register (see page 330). The baud-rate divisor (BRD) has the following relationship to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part, separated by a decimal place.)

BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate)

where UARTSysClk is the system clock connected to the UART.

The6-bitfractionalnumber(thatistobeloadedintothe DIVFRAC bitfieldinthe UARTFBRD register) can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 to account for rounding errors:

UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)

The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred to as Baud16). This reference clock is divided by 16 to generate the transmit clock, and is used for error detection during receive operations.

AlongwiththeUARTLineControl,HighByte(UARTLCRH) register(seepage331),theUARTIBRD and UARTFBRD registers form an internal 30-bit register. This internal register is only updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register for the changes to take effect.

To update the baud-rate registers, there are four possible sequences:

■UARTIBRD write, UARTFBRD write, and UARTLCRH write

■UARTFBRD write, UARTIBRD write, and UARTLCRH write

■UARTIBRD write and UARTLCRH write

■UARTFBRD write and UARTLCRH write

Preliminary

LM3S6965 Microcontroller

13.2.3Data Transmission

Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra fourbitspercharacterforstatusinformation. Fortransmission,dataiswrittenintothetransmitFIFO. If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated inthe UARTLCRH register. Datacontinuestobetransmitteduntilthereisnodataleftinthetransmit FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 326) is asserted as soon as data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits. The UART can indicate that it is busy even though the UART may no longer be enabled.

When the receiver is idle (the UnRx is continuously 1) and the data input goes Low (a start bit has been received), the receive counter begins running and data is sampled on the eighth cycle of Baud16 (described in “Transmit/Receive Logic” on page 315).

The start bit is valid if UnRx is still low on the eighth cycle of Baud16, otherwise a false start bit is detected and it is ignored. Start bit errors can be viewed in the UART Receive Status (UARTRSR) register (see page 324). If the start bit was valid, successive data bits are sampled on every 16th cycle of Baud16 (that is, one bit period later) according to the programmed length of the data characters. The parity bit is then checked if parity mode was enabled. Data length and parity are defined in the UARTLCRH register.

Lastly, a valid stop bit is confirmed if UnRx is High, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO, with any error bits associated with that word.

13.2.4Serial IR (SIR)

The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block provides functionality that converts between an asynchronous UART data stream, and half-duplex serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to provide a digital encoded output, and decoded input to the UART. The UART signal pins can be connected to an infrared transceiver to implement an IrDA SIR physical layer link. The SIR block has two modes of operation:

■In normal IrDA mode, a zero logic level is transmitted as high pulse of 3/16th duration of the selected baud rate bit period on the output pin, while logic one levels are transmitted as a static LOW signal. These levels control the driver of an infrared transmitter, sending a pulse of light foreachzero. Onthereceptionside,theincominglightpulsesenergizethephototransistorbase of the receiver, pulling its output LOW. This drives the UART input pin LOW.

■In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the period of the internally generated IrLPBaud16 signal (1.63 µs, assuming a nominal 1.8432 MHz frequency) by changing the appropriate bit in the UARTCR register. See page 328 for more information on IrDA low-power pulse-duration configuration.

Figure 13-3 on page 318 shows the UART transmit and receive signals, with and without IrDA modulation.

Preliminary

Universal Asynchronous Receivers/Transmitters (UARTs)

Figure 13-3. IrDA Data Modulation

In both normal and low-power IrDA modes:

■During transmission, the UART data bit is used as the base for encoding

■During reception, the decoded bits are transferred to the UART receive logic

TheIrDASIRphysicallayerspecifiesahalf-duplexcommunicationlink,withaminimum10msdelay between transmission and reception. This delay must be generated by software because it is not automaticallysupportedbytheUART. Thedelayisrequiredbecausetheinfraredreceiverelectronics mightbecomebiased,orevensaturatedfromtheopticalpowercoupledfromtheadjacenttransmitter LED. This delay is known as latency, or receiver setup time.

13.2.5FIFO Operation

The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed via the UART Data (UARTDR) register (see page 322). Read operations of the UARTDR register returna12-bitvalueconsistingof8databitsand4errorflagswhilewriteoperationsplace8-bitdata in the transmit FIFO.

Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are enabled by setting the FEN bit in UARTLCRH (page 331).

FIFOstatuscanbemonitoredviathe UART Flag (UARTFR) register(seepage326)andthe UART Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits) and the UARTRSR register shows overrun status via the OE bit.

The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO Level Select (UARTIFLS) register (see page 335). Both FIFOs can be individually configured to trigger interrupts at different levels. Available configurations include 1/8, ¼, ½, ¾, and 7/8. For example, if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the

½ mark.

13.2.6Interrupts

The UART can generate interrupts when the following conditions are observed:

■ Overrun Error

Preliminary