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LM3S6965 Microcontroller

Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0

This register defines the analog input configuration for a sample executed with Sample Sequencer 3.Thisregisteris4-bitswideandcontainsinformationforonepossiblesample.SeetheADCSSMUX0 register on page 301 for detailed bit descriptions.

ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3)

Base 0x4003.8000

Offset 0x0A0

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

MUX0

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

31:2

reserved

RO

0x0000.000

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

1:0

MUX0

R/W

0

1st Sample Input Select

November 16, 2008

311

Preliminary

Analog-to-Digital Converter (ADC)

Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4

This register contains the configuration information for a sample executed with Sample Sequencer 3. The END bit is always set since there is only one sample in this sequencer. This register is 4-bits wide and contains information for one possible sample. See the ADCSSCTL0 register on page 303 for detailed bit descriptions.

ADC Sample Sequence Control 3 (ADCSSCTL3)

Base 0x4003.8000

Offset 0x0A4

Type R/W, reset 0x0000.0002

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

reserved

 

 

 

 

 

TS0

IE0

END0

D0

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

Bit/Field

Name

Type

Reset

Description

31:4

reserved

RO

0x0000.000

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

3

TS0

R/W

0

1st Sample Temp Sensor Select

 

 

 

 

Same definition as TS7 but used during the first sample.

2

IE0

R/W

0

1st Sample Interrupt Enable

 

 

 

 

Same definition as IE7 but used during the first sample.

1

END0

R/W

1

1st Sample is End of Sequence

 

 

 

 

Same definition as END7 but used during the first sample.

 

 

 

 

Since this sequencer has only one entry, this bit must be set.

0

D0

R/W

0

1st Sample Diff Input Select

 

 

 

 

Same definition as D7 but used during the first sample.

312

November 16, 2008

Preliminary

LM3S6965 Microcontroller

Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100

This register provides loopback operation within the digital logic of the ADC, which can be useful in debugging software without having to provide actual analog stimulus. This test mode is entered by writing a value of 0x0000.0001 to this register. When data is read from the FIFO in loopback mode, the read-only portion of this register is returned.

ADC Test Mode Loopback (ADCTMLB)

Base 0x4003.8000

Offset 0x100

Type R/W, reset 0x0000.0000

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

LB

Type

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

R/W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit/Field

Name

Type

Reset

Description

 

31:1

reserved

RO

0x0000.000

Software should not rely on the value of a reserved bit. To provide

 

 

 

 

compatibility with future products, the value of a reserved bit should be

 

 

 

 

preserved across a read-modify-write operation.

0

LB

R/W

0

Loopback Mode Enable

 

 

 

 

Whenset,forcesaloopbackwithinthedigitalblocktoprovideinformation

 

 

 

 

on input and unique numbering. The ADCSSFIFOn registers do not

 

 

 

 

provide sample data, but instead provide the 10-bit loopback data as

 

 

 

 

shown below.

 

 

 

 

 

Bit/Field

Name

Description

 

 

 

 

9:6

CNT

Continuous Sample Counter

 

 

 

 

 

 

Continuous sample counter that is initialized to 0 and

 

 

 

 

 

 

counts each sample as it processed. This helps

 

 

 

 

 

 

provide a unique value for the data received.

 

 

 

 

5

CONT Continuation Sample Indicator

 

 

 

 

 

 

Whenset,indicatesthatthisisacontinuationsample.

 

 

 

 

 

 

For example, if two sequencers were to run

 

 

 

 

 

 

back-to-back, this indicates that the controller kept

 

 

 

 

 

 

continuously sampling at full rate.

 

 

 

 

4

DIFF

Differential Sample Indicator

 

 

 

 

 

 

When set, indicates that this is a differential sample.

 

 

 

 

3

TS

Temp Sensor Sample Indicator

 

 

 

 

 

 

When set, indicates that this is a temperature sensor

 

 

 

 

 

 

sample.

 

 

 

 

2:0

MUX

Analog Input Indicator

 

 

 

 

 

 

Indicates which analog input is to be sampled.

November 16, 2008

313

Preliminary

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