- •TABLE OF CONTENTS
- •Table of contents chapter 2
- •The WAGO I/O System
- •Buscoupler - INTERBUS S
- •Supply Voltage - Electronics
- •Supply Voltage - Field Side
- •Bus connection and station (node) address
- •The Enclosure and Specifications
- •INTERBUS S
- •Configuration software
- •Configuration of the fieldbus node in the master
- •Identification Code
- •ID Code for WAGO I/O System
- •IBS CMD configuration software
- •CMD Software Package
- •Example of an application
- •Buscoupler startup and troubleshooting
- •General conditions
- •Transporting and storing conditions
- •Mechanical and climatic conditions
- •Class of protection and degree of protection
- •Electromagnetic compatibility
- •Power supply
- •Certificates
- •SSI Encoder Interface
- •Quadrature Encoder Interface
- •Application in Explosive Environments
5.4 Example of an application
Ill. 19: Example of an application
The Interbus S station is composed as follows:
Function module |
Process image inputs |
Process image outputs |
1; Digital input |
PI 32.0 |
|
1; Digital Input |
PI 32.1 |
|
2; Digital Input |
PI 32.2 |
|
2; Digital Input |
PI 32.3 |
|
3; Voltage supply |
------ |
------ |
4; Analog Input |
PI 20 |
|
4; Analog Input |
PI 22 |
|
5; Voltage supply |
------ |
------ |
6; Digital Output |
|
PI28.0 |
6; Digital Output |
|
PI28.1 |
7; Digital Output |
|
PI28.2 |
7; Digital Output |
|
PI28.3 |
8; Digital Output |
|
PI28.4 |
8; Digital Output |
|
PI28.5 |
9; Digital Output |
|
PI28.6 |
9; Digital Output |
|
PI28.7 |
10; Voltage supply |
------ |
------ |
11; Analog Output |
|
PI 20 |
11; Analog Output |
|
PI 22 |
12; Analog Input |
PI 24 |
|
12; Analog Input |
PI 26 |
|
13; Analog Output |
|
PI 24 |
13; Analog Output |
|
PI 26 |
14; Analog Input |
PI 28 |
|
14; Analog Input |
PI 30 |
|
15; Voltage supply |
------ |
------ |
16; Digital Output |
|
PI29.0 |
16; Digital Output |
|
PI29.1 |
17; End module |
------ |
------ |
Table 5: Assignment of the process image
INTERBUS S / Configuration |
21 |
:$*2Ç, 2Ç6<67(0
The addresses indicated in the table results from the master configuration started in the basic address. By the internal structure of the Interbus coupler, the process image is divided as follows:
|
O0 |
|
Output data |
.... |
|
|
.....word orientated data |
|
|
.... |
|
|
Ox |
|
|
Ox+1 |
bit orientated data |
|
Ox+y |
|
|
|
|
|
|
|
|
I0 |
|
Input data |
.... |
|
|
....word orientated data |
|
|
.... |
|
|
Ix |
|
|
Ix+1 |
bit orientated data |
|
Ix+y |
|
|
|
|
Due to this division, the first addresses allocated in the configuration are reserved for the analog inputs and outputs. The counting direction is from left to right and starts with the first analog channel next to the bus coupler.
Ill. 21: Definition inputs/outputs
INTERBUS S / Configuration |
22 |
:$*2Ç, 2Ç6<67(0
