PIC12F683
12.0SPECIAL FEATURES OF THE CPU
The PIC12F683 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving features and offer code protection.
These features are:
•Reset
-Power-on Reset (POR)
-Power-up Timer (PWRT)
-Oscillator Start-up Timer (OST)
-Brown-out Reset (BOR)
•Interrupts
•Watchdog Timer (WDT)
•Oscillator Selection
•Sleep
•Code Protection
•ID Locations
•In-Circuit Serial Programming™
The PIC12F683 has two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 64 ms (nominal) on power-up only, designed to keep the part in Reset while the power supply stabilizes. There is also circuitry to reset the device if a brown-out occurs, which can use the Power-up Timer to provide at least a 64 ms Reset. With these three functions on-chip, most applications need no external Reset circuitry.
The Sleep mode is designed to offer a very low-current Power-down mode. The user can wake-up from Sleep through:
•External Reset
•Watchdog Timer Wake-up
•An interrupt
Several oscillator options are also made available to allow the part to fit the application. The INTOSC option saves system cost while the LP crystal option saves power. A set of Configuration bits are used to select various options (see Register 12-1).
Note: Address 2007h is beyond the user program memory space. It belongs to the special configuration memory space (2000h-3FFFh), which can be accessed only during programming. See “PIC12F6XX/16F6XX Memory Programming Specification” (DS41204) for more information.
12.1Configuration Bits
The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’) to select various device configurations as shown in Register 12-1. These bits are mapped in program memory location 2007h.
♥ 2007 Microchip Technology Inc. |
DS41211D-page 83 |
PIC12F683
REGISTER 12-1: CONFIG: CONFIGURATION WORD REGISTER
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— |
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— |
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— |
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— |
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FCMEN |
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IESO |
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BOREN1 |
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BOREN0 |
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bit 15 |
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bit 8 |
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CPD |
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CP |
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MCLRE |
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PWRTE |
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WDTE |
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FOSC2 |
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FOSC1 |
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FOSC0 |
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bit 7 |
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bit 0 |
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Legend: |
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R = Readable bit |
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W = Writable bit |
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P = Programmable’ |
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U = Unimplemented bit, read as ‘0’ |
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-n = Value at POR |
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‘1’ = Bit is set |
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‘0’ = Bit is cleared |
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x = Bit is unknown |
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bit 15-12 |
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Unimplemented: Read as ‘1’ |
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bit 11 |
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FCMEN: Fail-Safe Clock Monitor Enabled bit |
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1 |
= Fail-Safe Clock Monitor is enabled |
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0 |
= Fail-Safe Clock Monitor is disabled |
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bit 10 |
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IESO: Internal External Switchover bit |
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1 |
= Internal External Switchover mode is enabled |
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0 |
= Internal External Switchover mode is disabled |
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bit 9-8 |
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BOREN<1:0>: Brown-out Reset Selection bits(1) |
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11 = BOR enabled |
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10 = BOR enabled during operation and disabled in Sleep |
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01 = BOR controlled by SBOREN bit of the PCON register |
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00 = BOR disabled |
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Data Code Protection bit(2) |
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bit 7 |
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CPD: |
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1 |
= Data memory code protection is disabled |
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0 |
= Data memory code protection is enabled |
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Code Protection bit(3) |
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bit 6 |
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CP: |
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1 |
= Program memory code protection is disabled |
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0 |
= Program memory code protection is enabled |
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bit 5 |
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MCLRE: GP3/ |
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pin function select bit(4) |
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MCLR |
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1 |
= GP3/MCLR pin function is MCLR |
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pin function is digital input, |
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internally tied to VDD |
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0 |
= GP3/MCLR |
MCLR |
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bit 4 |
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PWRTE: Power-up Timer Enable bit |
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1 |
= PWRT disabled |
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0 |
= PWRT enabled |
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bit 3 |
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WDTE: Watchdog Timer Enable bit |
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1 |
= WDT enabled |
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0 |
= WDT disabled and can be enabled by SWDTEN bit of the WDTCON register |
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bit 2-0 |
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FOSC<2:0>: Oscillator Selection bits |
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111 = RC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN |
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110 = RCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN |
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101 = INTOSC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN |
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100 = INTOSCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN |
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011 = EC: I/O function on GP4/OSC2/CLKOUT pin, CLKIN on GP5/OSC1/CLKIN |
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010 = HS oscillator: High-speed crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN |
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001 = XT oscillator: Crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN |
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000 = LP oscillator: Low-power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN |
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Note 1: |
Enabling Brown-out Reset does not automatically enable Power-up Timer. |
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2:The entire data EEPROM will be erased when the code protection is turned off.
3:The entire program memory will be erased when the code protection is turned off.
4:When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
DS41211D-page 84 |
♥ 2007 Microchip Technology Inc. |