DAC8552
www.ti.com
SLAS430A – JULY 2006 – REVISED OCTOBER 2006
SERIAL WRITE OPERATION
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t1 |
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t9 |
SCLK |
1 |
24 |
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t8 |
t2 |
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t3 |
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t7 |
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t4 |
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SYNC |
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t6 |
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t5 |
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DIN |
DB23 |
DB0 |
DB23 |
TIMING CHARACTERISTICS(1) (2)
VDD = 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted).
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PARAMETER |
TEST CONDITIONS |
MIN TYP MAX |
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t (3) |
SCLK cycle time |
VDD = 2.7V to 3.6V |
50 |
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VDD = 3.6V to 5.5V |
33 |
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t2 |
SCLK HIGH time |
VDD = 2.7V to 3.6V |
13 |
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VDD = 3.6V to 5.5V |
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t3 |
SCLK LOW time |
VDD = 2.7V to 3.6V |
22.5 |
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VDD = 3.6V to 5.5V |
13 |
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t4 |
SYNC to SCLK rising edge setup time |
VDD = 2.7V to 3.6V |
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VDD = 3.6V to 5.5V |
0 |
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t5 |
Data setup time |
VDD = 2.7V to 3.6V |
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VDD = 3.6V to 5.5V |
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t6 |
Data hold time |
VDD = 2.7V to 3.6V |
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VDD = 3.6V to 5.5V |
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t7 |
24th SCLK falling edge to SYNC rising edge |
VDD = 2.7V to 3.6V |
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VDD = 3.6V to 5.5V |
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t8 |
Minimum SYNC HIGH time |
VDD = 2.7V to 3.6V |
50 |
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VDD = 3.6V to 5.5V |
33 |
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t9 |
24th SCLK falling edge to SYNC falling edge |
VDD = 2.7V to 5.5V |
100 |
ns |
(1)All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
(2)See Serial Write Operation Timing Diagram.
(3)Maximum SCLK frequency is 30MHz at VDD = 3.6V to 5.5V and 20MHz at VDD = 2.7V to 3.6V.
Submit Documentation Feedback |
5 |
DAC8552
www.ti.com
SLAS430A – JULY 2006 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS: VDD = 5V
At TA = +25°C, unless otherwise noted.
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LINEARITY ERROR AND |
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DIFFERENTIAL LINEARITY ERROR vs CODE |
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VDD = 5V, VREF = 4.9V, T |
A = +25° |
C |
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LE(LSB) |
4 |
Channel A Output |
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2 |
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0 |
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−2 |
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−4 |
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−6 |
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−8 |
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DLE(LSB) |
1.0 |
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0.5 |
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−0.5 |
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0 |
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−1.0 |
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08192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 1.
ZERO-SCALE ERROR vs TEMPERATURE
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7.5 |
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VDD = 5V |
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5.0 |
VREF = 4.99V |
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(mV) |
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2.5 |
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ScaleError |
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CH B |
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0 |
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−2.5 |
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Zero |
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CH A |
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−5.0 |
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−7.5 |
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−40 |
0 |
40 |
80 |
120 |
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Temperature (°C) |
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Figure 3.
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LINEARITY ERROR AND |
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DIFFERENTIAL LINEARITY ERROR vs CODE |
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8 |
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VDD = 5V, VREF = 4.9V, T |
A = +25° |
C |
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6 |
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4 |
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LE(LSB) |
Channel B Output |
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2 |
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0 |
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−2 |
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−4 |
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−6 |
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−8 |
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DLE(LSB) |
1.0 |
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0.5 |
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−0.5 |
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0 |
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−1.0 |
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08192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 2.
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FULL-SCALE ERROR |
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vs TEMPERATURE |
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5 |
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VDD = 5V |
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VREF = 4.99V |
(mV)ScaleError |
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CH B |
0 |
CH A |
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- |
−5 |
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Full |
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−10 |
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−40 |
0 |
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80 |
120 |
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Temperature (°C) |
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Figure 4.
SOURCE CURRENT CAPABILITY
AT POSITIVE RAIL
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6.0 |
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5.6 |
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(V) |
5.2 |
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OUT |
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V |
4.8 |
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4.4 |
VDD = 5.5V |
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VREF = VDD − 10mV |
DAC Loaded with FFFFh
4.0
0 |
2 |
4 |
6 |
8 |
10 |
ISOURCE (mA)
Figure 5.
SINK CURRENT CAPABILTY
AT NEGATIVE RAIL
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0.150 |
VREF = VDD − 10mV |
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0.125 |
DAC Loaded with 0000h |
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0.100 |
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(V) |
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VDD = 2.7V |
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OUT |
0.075 |
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V |
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VDD |
= 5.5V |
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0.050 |
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0.025 |
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0 |
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0 |
2 |
4 |
6 |
8 |
10 |
ISINK (mA)
Figure 6.
6 |
Submit Documentation Feedback |
DAC8552
www.ti.com
SLAS430A – JULY 2006 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS: VDD = 5V (continued)
At TA = +25°C, unless otherwise noted.
SUPPLY CURRENT |
SUPPLY CURRENT |
vs DIGITAL INPUT CODE |
vs SUPPLY VOLTAGE |
600 
Reference Current Included
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500 |
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VDD = VREF = 5.5V |
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400 |
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A) |
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VDD = VREF = 3.6V |
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300 |
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DD |
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I |
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200 |
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100 |
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0 |
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0 |
8192 |
16384 |
24576 32768 |
40960 |
49152 |
57344 |
65536 |
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Digital Input Code |
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600 |
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550 |
VREF = VDD, All DACs Powered |
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Reference Current Included, No Load |
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500 |
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( A) |
450 |
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400 |
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DD |
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I |
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350 |
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300 |
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250 |
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200 |
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2.7 |
3.1 |
3.5 |
4.3 |
4.7 |
5.1 |
5.5 |
VDD (V)
Figure 7. |
Figure 8. |
SUPPLY CURRENT vs TEMPERATURE
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600 |
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Reference Current Included |
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500 |
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VDD = VREF = 5.5V |
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400 |
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(µV) |
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VDD = VREF = 3.6V |
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300 |
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DD |
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I |
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200 |
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100 |
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0 |
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−40 |
0 |
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80 |
120 |
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Temperature (°C) |
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Figure 9.
POWER SPECTRAL DENSITY
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−10 |
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VDD = 5V |
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VREF = 4.096V |
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−30 |
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fOUT = 1kHz |
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f |
= 1MSPS |
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CLK |
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Gain(dB) |
−50 |
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−70 |
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−90 |
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−110 |
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−130 |
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0 |
5 |
10 |
15 |
20 |
Frequency (kHz)
Figure 11.
SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
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2400 |
TA = 25°C, SYNC Input (all other inputs = GND) |
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2000 |
CH A Powered Up; All Other Channels in Power-Down |
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1600 |
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A) |
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VDD = VREF = 5.5V |
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( |
1200 |
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DD |
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I |
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800 |
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400 |
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0 |
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0 |
1 |
2 |
3 |
4 |
5 |
5.5 |
VLOGIC (V)
Figure 10.
TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY
−40 VDD = 5V
−50 VREF = 4.9V -1dB FSR Digital Input
fS = 1MSPS
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−60 |
Measurement Bandwidth = 20kHz |
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(dB) |
−70 |
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THD |
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THD |
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−80 |
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−90 |
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2nd Harmonic |
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3rd Harmonic |
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−100 |
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0 |
1 |
2 |
3 |
4 |
5 |
fOUT (kHz)
Figure 12.
Submit Documentation Feedback |
7 |
DAC8552
www.ti.com
SLAS430A – JULY 2006 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS: VDD = 5V (continued)
At TA = +25°C, unless otherwise noted.
SIGNAL-TO-NOISE RATIO vs OUTPUT FREQUENCY
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98 |
VREF = VDD = 5V |
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96 |
-1dB FSR Digital Input |
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fS |
= 1MSPS |
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94 |
Measurement Bandwidth = 20kHz |
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SNR(dB) |
92 |
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90 |
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88 |
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86 |
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84 |
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0 |
0.5 |
1.0 |
1.5 |
2.0 |
2.5 |
3.0 |
3.5 |
4.0 |
4.5 |
5.5 |
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fOUT (kHz) |
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Figure 13.
FULL-SCALE SETTLING TIME: 5V RISING EDGE
Trigger Pulse 5V/div
VDD = 5V
VREF = 4.096V
From Code: D000
To Code: FFFF
Rising Edge
1V/div Zoomed Rising Edge
1mV/div
Time (2 s/div)
Figure 15.
HALF-SCALE SETTLING TIME: 5V RISING EDGE
Trigger Pulse 5V/div
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VDD = 5V |
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VREF = 4.096V |
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Rising |
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From Code: 4000 |
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Edge |
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To Code: CFFF |
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1V/div |
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Zoomed Rising Edge |
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1mV/div |
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Time (2 s/div)
Figure 17.
OUTPUT NOISE DENSITY
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350 |
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VDD = 5V |
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VREF = 4.99V |
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300 |
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Code = 7FFFh |
√Hz) |
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No Load |
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(nV/ |
250 |
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VoltageNoise |
200 |
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150 |
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100 |
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100 |
1k |
10k |
100k |
Frequency (Hz)
Figure 14.
FULL-SCALE SETTLING TIME: 5V FALLING EDGE
Trigger Pulse 5V/div
VDD = 5V
VREF = 4.096V
From Code: FFFF
To Code: 0000
Falling |
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Edge |
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Zoomed Falling Edge |
1V/div |
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1mV/div |
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Time (2 s/div)
Figure 16.
HALF-SCALE SETTLING TIME: 5V FALLING EDGE
Trigger Pulse 5V/div
VDD = 5V
VREF = 4.096V
From Code: CFFF
To Code: 4000
Falling |
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Edge |
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Zoomed Falling Edge |
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1V/div |
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1mV/div |
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Time (2 s/div)
Figure 18.
8 |
Submit Documentation Feedback |
DAC8552
www.ti.com
SLAS430A – JULY 2006 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS: VDD = 5V (continued)
At TA = +25°C, unless otherwise noted.
GLITCH ENERGY: 5V, 1LSB STEP, RISING EDGE
(500 V/div) |
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OUT |
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VDD = 5V |
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V |
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VREF = 4.096V |
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From Code: 7FFF |
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To Code: 8000 |
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Glitch: 0.08nV-s |
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Time (400ns/div)
Figure 19.
GLITCH ENERGY: 5V, 16LSB STEP, RISING EDGE
(500 V/div) |
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OUT |
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VDD = 5V |
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V |
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VREF = 4.096V |
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From Code: 8000 |
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To Code: 8010 |
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Glitch: 0.04nV-s |
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Time (400ns/div)
Figure 21.
GLITCH ENERGY: 5V, 256LSB STEP, RISING EDGE
(5mV/div) |
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OUT |
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VDD = 5V |
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VREF = 4.096V |
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V |
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From Code: 8000 |
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To Code: 80FF |
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Glitch: Not Detected |
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Theoretical Worst Case |
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Time (400ns/div) |
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Figure 23. |
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GLITCH ENERGY: 5V, 1LSB STEP, FALLING EDGE
(500 V/div) |
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OUT |
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VDD = 5V |
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VREF = 4.096V |
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V |
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From Code: 8000 |
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To Code: 7FFF |
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Glitch: 0.16nV-s |
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Measured Worst Case |
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Time (400ns/div) |
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Figure 20.
GLITCH ENERGY: 5V, 16LSB STEP, FALLING EDGE
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VDD = 5V |
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VREF = 4.096V |
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V/div) |
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From Code: 8010 |
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Glitch: 0.08nV-s |
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To Code: 8000 |
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(500 |
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OUT |
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V |
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Time (400ns/div)
Figure 22.
GLITCH ENERGY: 5V, 256LSB STEP, FALLING EDGE
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VDD = 5V |
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VREF = 4.096V |
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From Code: 80FF |
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(5mV/div) |
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To Code: 8000 |
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Glitch: Not Detected |
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Theoretical Worst Case |
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OUT |
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V |
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Time (400ns/div)
Figure 24.
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