Figure 24-5. Additional Scan Signal for the Two-wire Interface

24.5.3Scanning the RESET Pin

The RESET pin accepts 5V active low logic for standard reset operation, and 12V active high logic for High Voltage Parallel Programming. An observe-only cell as shown in Figure 24-6 is inserted both for the 5V reset signal; RSTT, and the 12V reset signal; RSTHV.

Figure 24-6. Observe-only Cell

FF1

0

D Q

1

From ClockDR

Previous

Cell

24.5.4Scanning the Clock Pins

The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscillator, External RC, External Clock, (High Frequency) Crystal Oscillator, Low Frequency Crystal Oscillator, and Ceramic Resonator.

Figure 24-7 shows how each Oscillator with external connection is supported in the scan chain. The Enable signal is supported with a general boundary-scan cell, while the Oscillator/Clock output is attached to an observe-only cell. In addition to the main clock, the Timer Oscillator is scanned in the same way. The output from the internal RC Oscillator is not scanned, as this Oscillator does not have external connections.

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Figure 24-7. Boundary-scan Cells for Oscillators and Clock Options

XTAL1/TOSC1 XTAL2/TOSC2

Table 24-4 summaries the scan registers for the external clock pin XTAL1, Oscillators with XTAL1/XTAL2 connections as well as 32 kHz Timer Oscillator.

Notes: 1. Do not enable more than one clock source as main clock at a time.

2.Scanning an Oscillator output gives unpredictable results as there is a frequency drift between the Internal Oscillator and the JTAG TCK clock. If possible, scanning an external clock is preferred.

3.The clock configuration is programmed by fuses. As a fuse is not changed run-time, the clock configuration is considered fixed for a given application. The user is advised to scan the same clock option as to be used in the final system. The enable signals are supported in the scan chain because the system logic can disable clock options in sleep modes, thereby disconnecting the Oscillator pins from the scan path if not provided. The INTCAP Fuses are not supported in the scan-chain, so the boundary scan chain can not make a XTAL Oscillator requiring internal capacitors to run unless the fuse is correctly programmed.

24.5.5Scanning the Analog Comparator

The relevant Comparator signals regarding Boundary-scan are shown in Figure 24-8. The Boundary-scan cell from Figure 24-9 is attached to each of these signals. The signals are described in Table 24-5.

The Comparator need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well.

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Figure 24-8. Analog Comparator

BANDGAP

REFERENCE

ACBG

ACO

AC_IDLE

ACME

ADCEN

ADC MULTIPLEXER

OUTPUT

Figure 24-9. General Boundary-scan Cell used for Signals for Comparator and ADC

From ClockDR UpdateDR

Previous

Cell

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24.5.6Scanning the ADC

Figure 24-10 shows a block diagram of the ADC with all relevant control and observe signals. The Boundary-scan cell from Figure 24-9 is attached to each of these signals. The ADC need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well.

Figure 24-10. Analog to Digital Converter

VCCREN

AREF

IREFEN

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The signals are described briefly in Table 24-6.

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Note: Incorrect setting of the switches in Figure 24-10 will make signal contention and may damage the part. There are several input choices to the S&H circuitry on the negative input of the output comparator in Figure 24-10. Make sure only one path is selected from either one ADC pin, Bandgap reference source, or Ground.

If the ADC is not to be used during scan, the recommended input values from Table 24-6 should be used. The user is recommended not to use the Differential Gain stages during scan. Switchcap based gain stages require fast operation and accurate timing which is difficult to obtain when used in a scan chain. Details concerning operations of the differential gain stage is therefore not provided.

The AVR ADC is based on the analog circuitry shown in Figure 24-10 with a successive approximation algorithm implemented in the digital logic. When used in Boundary-scan, the problem is usually to ensure that an applied analog voltage is measured within some limits. This can easily be done without running a successive approximation algorithm: apply the lower limit on the digital DAC[9:0] lines, make sure the output from the comparator is low, then apply the upper limit on the digital DAC[9:0] lines, and verify the output from the comparator to be high.

The ADC need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well.

When using the ADC, remember the following:

•The Port Pin for the ADC channel in use must be configured to be an input with pull-up disabled to avoid signal contention.

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•In Normal mode, a dummy conversion (consisting of 10 comparisons) is performed when enabling the ADC. The user is advised to wait at least 200 ns after enabling the ADC before controlling/observing any ADC signal, or perform a dummy conversion before using the first result.

•The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal low (Sample mode).

As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3 when the power supply is 5.0V and AREF is externally connected to VCC.

The recommended values from Table 24-6 are used unless other values are given in the algorithm in Table 24-7. Only the DAC and Port Pin values of the Scan-chain are shown. The column “Actions” describes what JTAG instruction to be used before filling the Boundary-scan Register with the succeeding columns. The verification should be done on the data scanned out when scanning in the data on the same row in the table.

Table 24-7. Algorithm for Using the ADC

Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock frequency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at least five times the number of scan bits divided by the maximum hold time, thold,max.

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24.6Boundary-scan Order

Table 24-8 shows the scan order between TDI and TDO when the Boundary-scan chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned in the opposite bit order of the other ports. Exceptions from the rules are the Scan chains for the analog circuits, which constitute the most significant bits of the scan chain regardless of which physical pin they are connected to. In Figure 24-3, PXn. Data corresponds to FF0, PXn. Control corresponds to FF1, and PXn. Pullup_enable corresponds to FF2. Bit 2, 3, 4, and 5 of Port C is not in the scan chain, since these pins constitute the TAP pins when the JTAG is enabled.

Table 24-8. ATmega16A Boundary-scan Order

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