24. IEEE 1149.1 (JTAG) Boundary-scan

24.1Features

•JTAG (IEEE std. 1149.1 Compliant) Interface

•Boundary-scan Capabilities According to the JTAG Standard

•Full Scan of all Port Functions as well as Analog Circuitry having Off-chip Connections

•Supports the Optional IDCODE Instruction

•Additional Public AVR_RESET Instruction to Reset the AVR

24.2Overview

The Boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having Off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by the TDI/TDO signals to form a long Shift Register. An external controller sets up the devices to drive values at their output pins, and observe the input values received from other devices. The controller compares the received data with the expected result. In this way, Boundary-scan provides a mechanism for testing interconnections and integrity of components on Printed Circuits Boards by using the four TAP signals only.

The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRELOAD, and EXTEST, as well as the AVR specific public JTAG instruction AVR_RESET can be used for testing the Printed Circuit Board. Initial scanning of the Data Register path will show the ID-code of the device, since IDCODE is the default JTAG instruction. It may be desirable to have the AVR device in Reset during Test mode. If not reset, inputs to the device may be determined by the scan operations, and the internal software may be in an undetermined state when exiting the Test mode. Entering reset, the outputs of any Port Pin will instantly enter the high impedance state, making the HIGHZ instruction redundant. If needed, the BYPASS instruction can be issued to make the shortest possible scan chain through the device. The device can be set in the reset state either by pulling the external RESET pin low, or issuing the AVR_RESET instruction with appropriate setting of the Reset Data Register.

The EXTEST instruction is used for sampling external pins and loading output pins with data. The data from the output latch will be driven out on the pins as soon as the EXTEST instruction is loaded into the JTAG IR-Register. Therefore, the SAMPLE/PRELOAD should also be used for setting initial values to the scan ring, to avoid damaging the board when issuing the EXTEST instruction for the first time. SAMPLE/PRELOAD can also be used for taking a snapshot of the external pins during normal operation of the part.

The JTAGEN Fuse must be programmed and the JTD bit in the I/O Register MCUCSR must be cleared to enable the JTAG Test Access Port.

When using the JTAG interface for Boundary-scan, using a JTAG TCK clock frequency higher than the internal chip frequency is possible. The chip clock is not required to run.

24.3Data Registers

The Data Registers relevant for Boundary-scan operations are:

•Bypass Register

•Device Identification Register

•Reset Register

•Boundary-scan Chain

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24.3.1Bypass Register

The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state. The Bypass Register can be used to shorten the scan chain on a system when the other devices are to be tested.

24.3.2Device Identification Register

Figure 24-1 shows the structure of the Device Identification Register.

Figure 24-1. The Format of the Device Identification Register

24.3.2.1Version

Version is a 4-bit number identifying the revision of the component. The JTAG version number follows the revision of the device. Revision A is 0x0, revision B is 0x1 and so on. However, some revisions deviate from this rule, and the relevant version number is shown in Table 24-1.

Table 24-1. JTAG Version Numbers

24.3.2.2Part Number

The part number is a 16-bit code identifying the component. The JTAG Part Number for

ATmega16A is listed in Table 24-2.

24.3.2.3Manufacturer ID

The Manufacturer ID is a 11 bit code identifying the manufacturer. The JTAG manufacturer ID for ATMEL is listed in Table 24-3.

24.3.3Reset Register

The Reset Register is a Test Data Register used to reset the part. Since the AVR tri-states Port

Pins when reset, the Reset Register can also replace the function of the unimplemented optional

JTAG instruction HIGHZ.

A high value in the Reset Register corresponds to pulling the External Reset low. The part is reset as long as there is a high value present in the Reset Register. Depending on the Fuse settings for the clock options, the part will remain reset for a Reset Time-Out Period (refer to “Clock

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Sources” on page 25) after releasing the Reset Register. The output from this Data Register is not latched, so the reset will take place immediately, as shown in Figure 24-2.

Figure 24-2. Reset Register

To

TDO

From other Internal and

External Reset Sources

ClockDR · AVR_RESET

24.3.4Boundary-scan Chain

The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having Off-chip connections.

See “Boundary-scan Chain” on page 235 for a complete description.

24.4Boundary-scan Specific JTAG Instructions

The instruction register is 4-bit wide, supporting up to 16 instructions. Listed below are the JTAG instructions useful for Boundary-scan operation. Note that the optional HIGHZ instruction is not implemented, but all outputs with tri-state capability can be set in high-impedant state by using the AVR_RESET instruction, since the initial state for all port pins is tri-state.

As a definition in this datasheet, the LSB is shifted in and out first for all Shift Registers.

The OPCODE for each instruction is shown behind the instruction name in hex format. The text describes which Data Register is selected as path between TDI and TDO for each instruction.

24.4.1EXTEST; $0

Mandatory JTAG instruction for selecting the Boundary-scan Chain as Data Register for testing circuitry external to the AVR package. For port-pins, Pull-up Disable, Output Control, Output Data, and Input Data are all accessible in the scan chain. For Analog circuits having Off-chip connections, the interface between the analog and the digital logic is in the scan chain. The contents of the latched outputs of the Boundary-scan chain is driven out as soon as the JTAG IRregister is loaded with the EXTEST instruction.

The active states are:

•Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.

•Shift-DR: The Internal Scan Chain is shifted by the TCK input.

•Update-DR: Data from the scan chain is applied to output pins.

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24.4.2IDCODE; $1

Optional JTAG instruction selecting the 32-bit ID-register as Data Register. The ID-register consists of a version number, a device number and the manufacturer code chosen by JEDEC. This is the default instruction after power-up.

The active states are:

•Capture-DR: Data in the IDCODE-register is sampled into the Boundary-scan Chain.

•Shift-DR: The IDCODE scan chain is shifted by the TCK input.

24.4.3SAMPLE_PRELOAD; $2

Mandatory JTAG instruction for pre-loading the output latches and talking a snap-shot of the input/output pins without affecting the system operation. However, the output latches are not connected to the pins. The Boundary-scan Chain is selected as Data Register.

The active states are:

•Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.

•Shift-DR: The Boundary-scan Chain is shifted by the TCK input.

•Update-DR: Data from the Boundary-scan Chain is applied to the output latches. However, the output latches are not connected to the pins.

24.4.4AVR_RESET; $C

The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or releasing the JTAG Reset source. The TAP controller is not reset by this instruction. The one bit Reset Register is selected as Data Register. Note that the reset will be active as long as there is a logic 'one' in the Reset Chain. The output from this chain is not latched.

The active states are:

• Shift-DR: The Reset Register is shifted by the TCK input.

24.4.5BYPASS; $F

Mandatory JTAG instruction selecting the Bypass Register for Data Register.

The active states are:

•Capture-DR: Loads a logic “0” into the Bypass Register.

•Shift-DR: The Bypass Register cell between TDI and TDO is shifted.

24.5Boundary-scan Chain

The Boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having Off-chip connection.

24.5.1Scanning the Digital Port Pins

Figure 24-3 shows the Boundary-scan Cell for a bi-directional port pin with pull-up function. The cell consists of a standard Boundary-scan cell for the Pull-up Enable – PUExn – function, and a bi-directional pin cell that combines the three signals Output Control – OCxn, Output Data – ODxn, and Input Data – IDxn, into only a two-stage Shift Register. The port and pin indexes are not used in the following description.

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The Boundary-scan logic is not included in the figures in the datasheet. Figure 24-4 shows a simple digital Port Pin as described in the section “I/O Ports” on page 49. The Boundary-scan details from Figure 24-3 replaces the dashed box in Figure 24-4.

When no alternate port function is present, the Input Data – ID – corresponds to the PINxn Register value (but ID has no synchronizer), Output Data corresponds to the PORT Register, Output Control corresponds to the Data Direction – DD Register, and the Pull-up Enable – PUExn – corresponds to logic expression PUD · DDxn · PORTxn.

Digital alternate port functions are connected outside the dotted box in Figure 24-4 to make the scan chain read the actual pin value. For Analog function, there is a direct connection from the external pin to the analog circuit, and a scan chain is inserted on the interface between the digital logic and the analog circuitry.

Figure 24-3. Boundary-scan Cell for Bidirectional Port Pin with Pull-up Function.

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Figure 24-4. General Port Pin Schematic Diagram(1)

Note: 1. See Boundary-scan description for details.

24.5.2Boundary-scan and the Two-wire Interface

The 2 Two-wire Interface pins SCL and SDA have one additional control signal in the scanchain; Two-wire Interface Enable – TWIEN. As shown in Figure 24-5, the TWIEN signal enables a tri-state buffer with slew-rate control in parallel with the ordinary digital port pins. A general scan cell as shown in Figure 24-9 is attached to the TWIEN signal.

Notes: 1. A separate scan chain for the 50 ns spike filter on the input is not provided. The ordinary scan support for digital port pins suffice for connectivity tests. The only reason for having TWIEN in the scan path, is to be able to disconnect the slew-rate control buffer when doing boundaryscan.

2.Make sure the OC and TWIEN signals are not asserted simultaneously, as this will lead to drive contention.

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