26.8Serial Downloading

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input), and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 26-11 on page 276, the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal SPI interface.

26.8.1SPI Serial Programming Pin Mapping

Table 26-11. Pin Mapping SPI Serial Programming

Figure 26-7. SPI Serial Programming and Verify(1)

RESET

GND

Notes: 1. If the device is clocked by the Internal Oscillator, it is no need to connect a clock source to the

XTAL1 pin.

2. VCC -0.3V < AVCC < VCC +0.3V, however, AVCC should always be within 2.7 - 5.5V

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into $FF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows:

Low: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck ≥ 12 MHz

High: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck ≥ 12 MHz

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26.8.2SPI Serial Programming Algorithm

When writing serial data to the ATmega16A, data is clocked on the rising edge of SCK.

When reading data from the ATmega16A, data is clocked on the falling edge of SCK. See Figure 27-5 for timing details.

To program and verify the ATmega16A in the SPI Serial Programming mode, the following sequence is recommended (See four byte instruction formats in Figure 26-13 on page 278):

1.Power-up sequence:

Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”.

2.Wait for at least 20 ms and enable SPI Serial Programming by sending the Programming Enable serial instruction to pin MOSI.

3.The SPI Serial Programming instructions will not work if the communication is out of synchronization. When in sync. the second byte ($53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the $53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command.

4.The Flash is programmed one page at a time. The page size is found in Table 26-5 on page 267. The memory page is loaded one byte at a time by supplying the 6 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data Low byte must be loaded before data High byte is applied for a given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 7 MSB of the address. If polling is not used,

the user must wait at least tWD_FLASH before issuing the next page. (See Table 26-12). Accessing the SPI Serial Programming interface before the Flash write operation completes can result in incorrect programming.

5.The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not used, the user must

wait at least tWD_EEPROM before issuing the next byte. (See Table 26-12). In a chip erased device, no $FFs in the data file(s) need to be programmed.

6.Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO.

7.At the end of the programming session, RESET can be set high to commence normal operation.

8.Power-off sequence (if needed): Set RESET to “1”.

Turn VCC power off.

26.8.3Data Polling Flash

When a page is being programmed into the Flash, reading an address location within the page being programmed will give the value $FF. At the time the device is ready for a new page, the programmed value will read correctly. This is used to determine when the next page can be written. Note that the entire page is written simultaneously and any address within the page can be used for polling. Data polling of the Flash will not work for the value $FF, so when programming

this value, the user will have to wait for at least tWD_FLASH before programming the next page. As a chip erased device contains $FF in all locations, programming of addresses that are meant to

contain $FF, can be skipped. See Table 26-12 for tWD_FLASH value

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26.8.4Data Polling EEPROM

When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value $FF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value $FF, but the user should have the following in mind: As a chip erased device contains $FF in all locations, programming of addresses that are meant to contain $FF, can be skipped. This does not apply if the EEPROM is re-programmed without chip erasing the device. In this case, data polling cannot be used for the value $FF, and

the user will have to wait at least tWD_EEPROM before programming the next byte. See Table 26-12 for tWD_EEPROM value.

Table 26-12. Minimum Wait Delay before Writing the Next Flash or EEPROM Location

26.8.5Serial Programming Instruction set

Table 26-13 on page 278 and Figure 26-8 on page 280 describes the Instruction set.

Table 26-13. Serial Programming Instruction Set (Hexadecimal values)

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Table 26-13. Serial Programming Instruction Set (Hexadecimal values) (Continued)

Notes: 1. Not all instructions are applicable for all parts.

2.a = address

3.Bits are programmed ‘0’, unprogrammed ‘1’.

4.To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) .

5.Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size.

6.See htt://www.atmel.com/avr for Application Notes regarding programming and programmers.

If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until this bit returns ‘0’ before the next instruction is carried out.

Within the same page, the low data byte must be loaded prior to the high data byte.

After data is loaded to the page buffer, program the EEPROM page, see Figure 26-8 on page 280.

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