Initial

begin

reset=1'b0; clk=1'b0;

#12 reset = 1;

#10 data_in=B;

#10 data_in=B;

#10 data_in=B;

#10 data_in=C;

#10 data_in=A;

#10 data_in=B;

#20 data_in = A;

#20 data_in = C;

#10 data_in = B;

#20 data_in = C;

#10 data_in = A;

#10 data_in = B;

#30 data_in = C;

#15 $finish;

end

always #5 clk=~clk;

endmodule

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