Task 1.2.
Design a circuit of the device that performs the conversion of a binary-coded decimal code given by weights of number positions (column “Input code”- Table3), in one of the given codes presented in Table2.
Table3
Number of variant |
Input code
|
Output code |
1 |
8421 |
Code with excess 3 |
2 |
8421 |
Code 2 out of 5 |
3 |
8421 |
Biquinary code |
4 |
2421 |
Code with excess 3 |
5 |
2421 |
Code 2 out of 5 |
6 |
2421 |
Biquinary code |
7 |
5211 |
Code with excess 3 |
8 |
5211 |
Code 2 out of 5 |
9 |
5211 |
Biquinary code |
10 |
4311 |
Code with excess 3 |
11 |
4311 |
Code 2 out of 5 |
12 |
4311 |
Biquinary code |
13 |
532-1 |
Code with excess 3 |
14 |
753-6 |
Code with excess 3 |
15 |
631-1 |
Code with excess 3 |
16 |
641-2 |
Code with excess 3 |
17 |
643-2 |
Code with excess 3 |
18 |
Code with excess 3 |
753-6 |
19 |
Code with excess 3 |
4311 |
20 |
Code with excess 3 |
532-1 |
Task 1.3.
Design a circuit of controlling seven-segment display
The indicators of such type on light diodes or liquid crystals are applied in calculators, clocks and measuring devices intended for display of data in decimal system.
To control the seven-segment display, combinational logic circuit with 4 inputs and 7 outputs is used (seven-segment decoder).
Fig.1. The structure of seven-segment decoder
Seven outputs of the circuit are connected to control electrodes of segments consisting of light diodes, which are lit at occurrence of signal "1". A digit is displayed by illuminating a subset of the seven line segments shown in Fig. 2 and Fig.3.
The seven-segment code is presented in Fig. 2.
Fig.2. Designation for the seven segments
The active segments for displaying each decimal digit are presented in Fig. 3.
Fig.3. Numbers formed by seven segments
Tasks are given in Table 4.
Task 1.3
Table 4.
Number of variant |
Binary-decimal code |
1. |
8421 |
2. |
7421 |
3. |
5321 |
4. |
5211 |
5. |
3321 |
6. |
2421 |
7. |
731-2 |
8. |
642-1 |
9. |
532-1 |
10. |
4311 |
11. |
631-1 |
12. |
753-6 |
13. |
543-2 |
14. |
632-2 |
15 |
641-2 |
16 |
643-2 |
17 |
642-3 |
18 |
5421 |
Task 1.4.
Design a circuit of a device to detect the following input binary numbers:
a) Simple numbers
b) Numbers, multiple 3
c) Numbers, the sum ones of which is even number
d) Numbers, the number of ones of which is equal 3
The number of bits input code equal to 5.
Task 1.5.
Design a circuit of a device for multiplication of integer two-bit unsigned numbers.
Task 1.6.
Design a circuit of a device for conversion of a four-bit binary code to a binary-coded decimal code in the output. The number of decimal bits is equal to two.
The circuit to transform binary code into binary-coded decimal will have 4 inputs and eight outputs. The structure of such a device is shown in Fig.4.
Fig. 4. The structure of device
Tetrad is called 4-bit binary code put in conformity to each decimal number.
The weights of input code are presented in Table 5.
Table 5
Number of variant |
Weight of code number P1P2 P3 P4 |
1. |
8 4 2 1 |
2. |
2 4 2 1 |
3. |
Code with excess 3 |
Task 1.7
Design a circuit of the device which carries out addition of unit to input number BCD (modulo 10).
Sequence of designing combinational circuit and content of an explanatory note
Content of the task
Composition of the table of input and output codes
Composition of the table of implementing functions
Minimization of functions with the help of Karnaugh maps
Transition in NAND and NOR bases
Design of circuits of the device in bases:
AND, OR, NOT,
NAND
NOR
Definition of polynomials of implementing functions
Implementation of the circuit of the device with a decoder
Implementation of the circuit of the device with multiplexers
At designing a circuit with multiplexers, be guided by the minimized values of functions. If the number of variables of function after minimization equals k, use the multiplexer with k-1 number of select inputs.
Gate-level netlist of designed circuit. Simulate using VCS.
Behavioral description of designed circuit
Synthesize the circuit with the help of Design Compiler. Use SAED EDK32/28nm technology library.
