- •Overview
- •What makes up a PDK?
- •Installation of the PDK
- •PDK Install Directory Structure/Contents
- •Creation of a Design Project
- •Techfile Methodology
- •Schematic Design
- •Library Device Setup
- •Resistors
- •Capacitors
- •MOSFETS
- •Bipolar Transistors
- •Inductor
- •Supported Devices
- •MOSFETS
- •RESISTORS
- •CAPACITORS
- •INDUCTOR
- •BIPOLARS
- •DIODES
- •Views provided
- •MOSFETS
- •RESISTORS
- •CAPACITORS
- •INDUCTOR
- •BIPOLARS
- •DIODES
- •CDF parameters
- •MOSFETS
- •RESISTORS
- •CAPACITORS
- •INDUCTOR
- •BIPOLARS
- •DIODES
- •Component Label Defaults
- •MOSFETS
- •RESISTORS
- •CAPACITORS
- •INDUCTORS
- •BIPOLARS
- •DIODES
- •Spectre Models
- •Techfile Layers
- •Virtuoso XL
- •SYMBOLIC CONTACTS
- •Dracula Support
- •Diva Decks
- •DIVA DRC
- •DIVA EXTRACT
- •DIVA LVS
- •DIVA LPE/PRE
- •Assura Decks
- •Assura DRC
- •Assura LVS
- •Assura RCX
- •DEVICE SPECIFICATIONS
- •Data Source Table
- •Model and Layout Source
- •MOS FORMAL PARAMETERS
- •RESISTOR FORMAL PARAMETERS
- •CAPACITOR FORMAL PARAMETERS
- •INDUCTOR FORMAL PARAMETERS
- •BIPOLAR FORMAL PARAMETERS
- •DIODES FORMAL PARAMETERS
- •DEVICE DATASHEETS
- •nmos – Nmos Transistor
- •nmos (backend)
- •nmos3 (backend)
- •pmos – Pmos Transistor
- •pmos (backend)
- •pmos3 – Pmos Transistor
- •pmos3 (backend)
- •nplusres – Nplus Resistor
- •nplusres (backend)
- •polyres – Poly Resistor
- •polyres (backend)
- •mimcap – Metal to Metal Capacitor
- •mimcap (backend)
- •nmoscap – Nmos Transistor Configured as Cap
- •nmoscap (backend)
- •inductor – Metal 3 Inductor
- •inductor (backend)
- •vpnp – Vertical Bipolar PNP
- •vpnp (backend)
- •npn – Bipolar npn
- •npn (backend)
- •pnp – Bipolar pnp
- •pnp (backend)
- •ndio – N type Diode
- •ndio (backend)
- •pdio – N type Diode
- •pdio (backend)
- •DESIGN RULES
- •Layout Guidelines
- •Density Rules
- •Interconnect Capacitance Table
- •Coupling Capacitance Table
- •Sheet Resistance Table
21.11npn – Bipolar npn
Spectre Netlist
Spectre Model Name = “npn”
Q1 ( C B E ) npn area=1 m=1
DIVA LVS Netlist
DIVA Device Name = “npn”
; npn Instance /Q1 = auLvs device Q1 d npn C B E
i 1 npn C B E " area 360e-3 m 1.0 "
CDL Netlist
CDL Device Name = “NP”
QQ1 C B E NP $EA=0.36
Assura Netlist Assura auLvs Device Name = “npn”
c npn BJT COLLECTOR B BASE B |
EMITTER B ;; |
* 3 pins |
|
* 3 nets |
|
* 0 instances |
|
i Q1 npn C B E ; area 0.36 m 1 ; |
|
npn (backend)
E |
B |
C |
|
Area |
|
|
Device Layers |
Layer |
Color and Fill |
|
|
NPNdummy
Nburied
Pwell
Nimp / Oxide
Pimp / Oxide
Cont
Metal1
|
Device Derivation |
Device |
Layer Derivation |
Recognition |
NPNdummy AND Nimp AND Pwell |
E |
NPNdummy AND Nburied AND Nimp AND Pwell |
B |
NPNdummy AND Nburied AND Pimp AND Pwell |
C |
NPNdummy AND Nburied AND Nimp ANDNOT Pwell |
|
LVS Comparison |
Parameter |
Calculation |
area |
Area of Emitter (illustrated above) |
21.12pnp – Bipolar pnp
Spectre Netlist
Spectre Model Name = “pnp”
Q1 ( C B E ) pnp area=1 m=1
DIVA LVS Netlist
DIVA Device Name = “pnp”
; pnp Instance /Q1 = auLvs device Q1 d pnp C B E
i 1 pnp C B E " area 360e-3 m 1.0 "
CDL Netlist
CDL Device Name = “PN”
QQ1 C B E PN $EA=0.36
Assura Netlist Assura auLvs Device Name = “pnp”
c pnp BJT COLLECTOR B BASE B |
EMITTER B ;; |
* 3 pins |
|
* 3 nets |
|
* 0 instances |
|
i Q1 pnp C B E ; area 0.36 m 1 ; |
|
pnp (backend)
E |
B |
C |
|
Area |
|
|
Device Layers |
Layer |
Color and Fill |
|
|
PNPdummy
Nburied
Nwell
Pwell
Nimp / Oxide
Pimp / Oxide
Cont
Metal1
|
Device Derivation |
Device |
Layer Derivation |
Recognition |
PNPdummy AND Pimp AND Pwell |
E |
PNPdummy AND Nburied AND Pimp AND Nwell |
B |
PNPdummy AND Nburied AND Nimp AND Nwell |
C |
PNPdummy AND Nburied AND Pimp ANDNOT Nwell |
|
LVS Comparison |
Parameter |
Calculation |
area |
Area of Emitter (illustrated above) |
