19 Assura Decks

Cadence has developed the Assura DRC, LVS, and RCX rule files from the documentation provided.

These decks can be found in the extracted PDK directory tree in the directory:

•assura_gpdk_tech

The user needs the licenses for these tools to perform verification. When performing verification you have to provide the library name to the verification deck. Select the desired switches before starting the verification run. Refrain from working on the target layout being verified while the run is in progress.

19.1 Assura DRC

The Assura DRC file provided is named

• drc.rul

The following switches are available in the Assura DRC file:

• Skip_Latch-Up_Checks - Switch to turn off DRC checks for body tie distance to MOS devices.

ASSURA DRC FORM

19.2 Assura LVS

The Assura LVS files provided are located in the gpdk_tech directory and named

•extract.rul

•compare.rul

The following switches are available in the Assura extract file:

• Skip_Soft-Connect_Checks - Select the switch to turn on the creation of markers for connections that are made through nwell or substrate

ASSURA LVS FORM