Поведенческое описание
entity test_kurs is end test_kurs;
use std.textio.all;
architecture test of test_kurs is
signal q1,q2:bit_vector(1 to 4);
signal r:bit_vector(1 to 2);
signal c,ct:bit_vector(1 to 2);
signal d:bit_vector(1 to 2);
signal g1,g2,g3,g4,g5,g6: bit_vector (1 to 20);
begin
process
variable j: integer:=0;
variable l: line;
begin
if j=20 then j:=1; else j:=j+1; end if;
g1(1 to 20):= "00000000000001110011"; -- r1
g2(1 to 20):= "10000000011101100010"; -- r2
g3(1 to 20):= "10101010010101010100"; -- c(1)
g4(1 to 20):= "10101010010101010100"; -- c(2)
g5(1 to 20):= "00010001010001100001"; -- d(1)
g6(1 to 20):= "01110101101110100000"; -- d(2)
r(1):=g1(j);r(2):=g2(j);
c(1):=g3(j);c(2):=g4(j);d(1):=g5(j);d(2):=g6(j);
if r(1)= '1' then q1(1):='0';q1(2):='0';q1(3):='0';q1(4):='0';
else
if (c(1) = '0' and ct(1) = '1') then
q1(4) := q1(3);q1(3) := q1(2);q1(2) := q1(1);q1(1) := d(1);
end if; end if;
ct(1) := c(1);
if r(2) = '1' then q2(1):='0';q2(2):='0';q2(3):='0';q2(4):='0';
else
if (c(2) = '0' and ct(2) = '1') then
q2(4) := q2(3);q2(3) := q2(2);q2(2) := q2(1);q2(1) := d(2);
end if;end if;
ct(2) := c(2);
if now=0ns then write (l,"Time |D1,2 | R1,2 | C1,2 | Q10,11,12,13| Q20,21,22,23");writeline(output,l);end if;;
write(l,now);write(l," | ");
write(l, d);write(l," | ");
write(l,r);write(l," | ");
write(l,c);write(l," | ");
write(l,q1);write(l," | ");
write(l,q2);write(l," | ");
writeline (output,l);
wait for 10ns;
end process;
end test;
Процедурное моделирование: файл test.vhd
library registr;
use registr.all;
use STD.TEXTIO.all;
entity test_kurs is
end test_kurs;
architecture test of test_kurs is
signal r,d,c:bit_vector(1 to 2);
signal q1,q2:bit_vector(1 to 4);
component kur
port(r,d,c:in bit_vector(1 to 2);q1,q2:out bit_vector(1 to 4));
end component;
for all:kur use entity registr.kurs(kurs_reg);
begin
device : kur port map(r,d,c,q1,q2);
c<=('1','1') after 0ns,('1','1') after 20ns,('0','0') after
30ns, (‘1’,’1’) after 40ns;
d(2)<='1' after 10ns,'0' after 40ns;
d(1)<='1' after 10ns,'0' after 20ns;
r<=('1','1') after 0ns,('0','0') after 10ns,('1','1') after
40ns;
process
variable l:line;
begin
write(l,"--------------------------------------------------------
---------------------");
writeline(output,l);
write(l,"time |d1,2 |r1,2 |c1,2 | Q10,11,12,13 | Q20,21,22,23 ");
writeline(output,l);
write(l,"--------------------------------------------------------
---------------------");
writeline(output,l);
wait for 1100ns;
end process;
process
variable t:time;
variable l:line;
begin
t:=now;
if t>1ns then
write(l,t);write(l," ");write(l,d(1));write(l,d(2));
write(l," ");
write(l,r(1));write(l,r(2));write(l," ”);write(l,c(1));
write(l,c(2));write(l," ");
write(l,q1(1));write(l," ");write(l,q1(2));write(l," ");
write(l,q1(3));write(l," ");
write(l,q1(4));write(l," ");write(l,q2(1));write(l," ");
write(l,q2(2));write(l," ");write(l,q2(3));
write(l," ");write(l,q2(4));writeline(output,l);
end if;
if t<200ns then wait for 10ns;else wait for 9ns; end if;
end process;
end test;
Содержание bat файла:
vhdl kurs.vhd
link kurs kurs test_kurs
sv 200ns kurs
ТАБЛИЦА ИСТИННОСТИ
Time |D1,2 | R1,2 | C1,2 | Q10,11,12,13| Q20,21,22,23