- •FEATURES
- •APPLICATIONS
- •DESCRIPTION
- •ABSOLUTE MAXIMUM RATINGS
- •RECOMMENDED OPERATING CONDITIONS
- •ELECTRICAL CHARACTERISTICS
- •ELECTRICAL CHARACTERISTICS
- •DIGITAL CHARACTERISTICS
- •TIMING CHARACTERISTICS – LVDS AND CMOS MODES
- •DEVICE PROGRAMMING MODES
- •USING SERIAL INTERFACE PROGRAMMING ONLY
- •USING PARALLEL INTERFACE CONTROL ONLY
- •SERIAL INTERFACE
- •REGISTER INITIALIZATION
- •SERIAL INTERFACE TIMING
- •RESET TIMING
- •SERIAL REGISTER MAP
- •DESCRIPTION OF SERIAL REGISTERS
- •TYPICAL CHARACTERISTICS - ADS6125 (FS= 125 MSPS)
- •TYPICAL CHARACTERISTICS - ADS6124 (FS= 105 MSPS)
- •TYPICAL CHARACTERISTICS - ADS6123 (FS= 80 MSPS)
- •TYPICAL CHARACTERISTICS - ADS6122 (FS= 65 MSPS)
- •TYPICAL CHARACTERISTICS - LOW SAMPLING FREQUENCIES
- •FS = 40 MSPS
- •FS = 25 MSPS
- •COMMON PLOTS
- •Contour Plots Across Input and Sampling Frequencies
- •APPLICATION INFORMATION
- •THEORY OF OPERATION
- •ANALOG INPUT
- •Drive Circuit Requirements
- •Using RF-Transformer Based Drive Circuits
- •Using Differential Amplifier Drive Circuits
- •Input Common-Mode
- •REFERENCE
- •Internal Reference
- •External Reference
- •COARSE GAIN and PROGRAMMABLE FINE GAIN
- •CLOCK INPUT
- •POWER DOWN MODES
- •Global Powerdown
- •Standby
- •Output Buffer Disable
- •Input Clock Stop
- •Power Supply Sequence
- •DIGITAL OUTPUT INTERFACE
- •Parallel CMOS Interface
- •DDR LVDS Interface
- •Output Data Format
- •Output Timings
- •BOARD DESIGN CONSIDERATIONS
- •Grounding
- •Supply Decoupling
- •Exposed Thermal Pad
- •DEFINITION OF SPECIFICATIONS
- •Analog Bandwidth
- •Aperture Delay
- •Aperture Uncertainty (Jitter)
- •Clock Pulse Width/Duty Cycle
- •Maximum Conversion Rate
- •Minimum Conversion Rate
- •Differential Nonlinearity (DNL)
- •Integral Nonlinearity (INL)
- •Gain Error
- •Offset Error
- •Temperature Drift
- •Signal-to-Noise Ratio
- •Signal-to-Noise and Distortion (SINAD)
- •Effective Number of Bits (ENOB)
- •Total Harmonic Distortion (THD)
- •Spurious-Free Dynamic Range (SFDR)
- •Two-Tone Intermodulation Distortion
- •DC Power Supply Rejection Ratio (DC PSRR)
- •AC Power Supply Rejection Ratio (AC PSRR)
- •Common Mode Rejection Ratio (CMRR)
- •Voltage Overload Recovery
ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER 2007–REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6125 (FS= 125 MSPS)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted)
Amplitude − dB
0
−20
−40
−60
−80
−100
−120
−140
−160
FFT for 20 MHz INPUT SIGNAL
SFDR = 92 dBc
SINAD = 71.3 dBFS
SNR = 71.5 dBFS
THD = 87.9 dBc
0 |
10 |
20 |
30 |
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60 |
f − Frequency − MHz
G001
Figure 9.
Amplitude − dB
0
−20
−40
−60
−80
−100
−120
−140
−160
FFT for 70 MHz INPUT SIGNAL
SFDR = 84.2 dBc
SINAD = 70.6 dBFS
SNR = 71 dBFS
THD = 82.7 dBc
0 |
10 |
20 |
30 |
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60 |
f − Frequency − MHz
G002
Figure 10.
Amplitude − dB
0
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−100
−120
−140
−160
FFT for 230 MHz INPUT SIGNAL |
INTERMODULATION DISTORTION (IMD) vs FREQUENCY |
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SFDR = 74.1 dBc |
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fIN1 = 190.1 MHz, ±7 dBFS |
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SINAD = 66.5 dBFS |
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fIN2 = 185.3 MHz, ±7 dBFS |
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SNR = 68.6 dBFS |
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2-Tone IMD = ±83.6 dBFS |
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THD = 71.4 dBc |
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SFDR = ±81.3 dBFS |
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− dB |
−60 |
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Amplitude |
−80 |
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−100 |
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−120 |
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−140 |
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−160 |
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f − Frequency − MHz |
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G003 |
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f − Frequency − MHz |
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G004 |
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Figure 11. |
Figure 12. |
SFDR vs INPUT FREQUENCY |
SNR vs INPUT FREQUENCY |
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76 |
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88 |
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74 |
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84 |
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72 |
− dBc |
80 |
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Gain = 3.5 dB |
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dBFS |
70 |
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SFDR |
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SNR − |
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76 |
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68 |
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72 |
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Gain = 0 dB |
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66 |
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68 |
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64 |
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64 |
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62 |
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0 |
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fIN − Input Frequency − MHz |
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G005 |
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Gain = 0 dB |
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Gain = 3.5 dB |
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fIN − Input Frequency − MHz |
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G006 |
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Figure 13. |
Figure 14. |
Copyright © 2007–2008, Texas Instruments Incorporated |
Submit Documentation Feedback |
25 |
Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122
ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER 2007–REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6125 (FS= 125 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted)
SFDR vs INPUT FREQUENCY (LVDS interface) |
SNR vs INPUT FREQUENCY (LVDS interface) |
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76 |
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88 |
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Gain = 3.5 dB |
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72 |
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− dBc |
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dBFS |
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80 |
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70 |
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SFDR |
76 |
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SNR − |
68 |
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Gain = 0 dB |
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66 |
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68 |
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64 |
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62 |
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fIN − Input Frequency − MHz |
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G007 |
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Gain = 0 dB |
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Gain = 3.5 dB |
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fIN − Input Frequency − MHz |
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G008 |
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Figure 15. |
Figure 16. |
SFDR vs INPUT FREQUENCY ACROSS GAINS |
SINAD vs INPUT FREQUENCY ACROSS GAINS |
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76 |
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Input adjusted to get −1dBFS input |
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3 dB |
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72 |
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5 dB |
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dBFS |
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dBc |
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70 |
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80 |
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6 dB |
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− |
68 |
SFDR |
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4 dB |
SINAD |
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75 |
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0 dB |
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66 |
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1 dB |
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64 |
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2 dB |
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62 |
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60 |
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fIN − Input Frequency − MHz |
G009 |
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Input adjusted to get −1dBFS input |
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0 dB |
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1 dB |
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2 dB |
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3 dB |
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4 dB |
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6 dB |
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5 dB |
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fIN |
− Input Frequency − MHz |
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G010 |
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Figure 17. |
Figure 18. |
SFDR − dBc
PERFORMANCE vs AVDD |
PERFORMANCE vs DRVDD |
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78 |
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96 |
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73 |
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86 |
fIN = 70.1 MHz |
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77 |
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fIN = 10.1 MHz |
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DRVDD = 3.3 V |
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SFDR |
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94 |
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AVDD = 3.3 V |
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72 |
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84 |
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76 |
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SNR |
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dBFS |
dBc− |
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dBFS |
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75 |
92 |
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71 |
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80 |
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74 |
SNR− |
SFDR |
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SNR− |
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73 |
90 |
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70 |
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SFDR |
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76 |
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SNR |
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72 |
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88 |
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69 |
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74 |
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71 |
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72 |
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70 |
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86 |
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68 |
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3.0 |
3.1 |
3.2 |
3.3 |
3.4 |
3.5 |
3.6 |
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1.8 |
2.0 |
2.2 |
2.4 |
2.6 |
2.8 |
3.0 |
3.2 |
3.4 |
3.6 |
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AV |
− Supply V oltage − V |
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DRVDD − Supply V oltage − V |
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G012 |
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DD |
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G011 |
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Figure 19. |
Figure 20. |
26 |
Submit Documentation Feedback |
Copyright © 2007–2008, Texas Instruments Incorporated |
Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122
ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER 2007–REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6125 (FS= 125 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted)
PERFORMANCE vs TEMPERATURE |
PERFORMANCE vs INPUT AMPLITUDE |
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94 |
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74 |
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110 |
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100 |
SFDR (dBFS) |
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92 |
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SFDR |
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dBc−SFDR |
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dBFS−SNR |
dBFSdBc,−SFDR |
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90 |
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SNR (dBFS) |
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SNR |
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70 |
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88 |
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71 |
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60 |
SFDR (dBc) |
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86 |
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fIN = 10.1 MHz |
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fIN = 10.1 MHz |
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−40 |
−20 |
0 |
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80 |
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−60 |
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−10 |
0 |
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T − T emperature − °C |
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G013 |
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Input Amplitude − dBFS |
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Figure 21. |
Figure 22. |
90 |
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− dBFS |
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SNR |
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55 |
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50
G014
PERFORMANCE vs CLOCK AMPLITUDE |
PERFORMANCE vs INPUT CLOCK DUTY CYCLE |
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72.0 |
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92 |
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fIN = 20.1 MHz |
SNR |
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91 |
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88 |
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71.0 |
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90 |
− dBc |
86 |
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70.5 |
dBFS |
− dBc |
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84 |
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SFDR |
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70.0 |
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SFDR |
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SNR − |
SFDR |
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69.5 |
87 |
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69.0 |
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86 |
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68.5 |
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85 |
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68.0 |
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0.5 |
1.0 |
1.5 |
2.0 |
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3.0 |
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Input Clock Amplitude − V PP |
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G015 |
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72.0 |
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SFDR |
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71.5 |
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71.0 |
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70.5 |
− dBFS |
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SNR |
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70.0 |
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SNR |
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69.5 |
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69.0 |
|
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fIN = 10.1 MHz |
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68.5 |
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68.0 |
|
30 |
35 |
40 |
45 |
50 |
55 |
60 |
65 |
70 |
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Input Clock Duty Cycle − % |
|
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G016 |
||
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Figure 23. |
Figure 24. |
Occurence − %
OUTPUT NOISE HISTOGRAM |
PERFORMANCE IN EXTERNAL REFERENCE MODE |
(INPUTS TIED TO COMMON-MODE) |
60 |
|
93 |
fIN = 20.1 MHz |
|
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|
76 |
|
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RMS (LSB) = 0.497 |
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50 |
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External Reference Mode |
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91 |
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74 |
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||
40 |
dBc− |
|
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SNR |
|
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dBFS |
|
89 |
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72 |
|||
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30 |
SFDR |
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SNR− |
|
87 |
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70 |
||
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20 |
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SFDR |
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10 |
|
85 |
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68 |
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0 |
|
83 |
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66 |
|
2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 |
|
1.30 |
1.35 |
1.40 |
1.45 |
1.50 |
1.55 |
1.60 |
1.65 |
1.70 |
|
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|||||||||
Output Code |
G017 |
|
|
VVCM − VCM V oltage − V |
|
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|
G018 |
|||
Figure 25. |
Figure 26. |
Copyright © 2007–2008, Texas Instruments Incorporated |
Submit Documentation Feedback |
27 |
Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122
ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER 2007–REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6124 (FS= 105 MSPS)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted)
Amplitude − dB
0
−20
−40
−60
−80
−100
−120
−140
−160
FFT for 20 MHz INPUT SIGNAL
SFDR = 88.2 dBc
SINAD = 71.3 dBFS
SNR = 71.5 dBFS
THD = 87.1 dBc
0 |
10 |
20 |
30 |
40 |
50 |
f − Frequency − MHz
G019
Figure 27.
Amplitude − dB
0
−20
−40
−60
−80
−100
−120
−140
−160
0
FFT for 80 MHz INPUT SIGNAL
SFDR = 84.8 dBc
SINAD = 70.8 dBFS
SNR = 71.1 dBFS
THD = 82.9 dBc
10 |
20 |
30 |
40 |
50 |
f − Frequency − MHz
G020
Figure 28.
Amplitude − dB
0
−20
−40
−60
−80
−100
−120
−140
−160
FFT for 230 MHz INPUT SIGNAL |
INTERMODULATION DISTORTION (IMD) vs FREQUENCY |
|
|
|
|
SFDR = 74.9 dBc |
|
0 |
|
|
fIN1 = 190.1 MHz, ±7 dBFS |
||
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||||
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SINAD = 65.8 dBFS |
|
−20 |
|
|
fIN2 = 185.3 MHz, ±7 dBFS |
||
|
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|
|
SNR = 67.1 dBFS |
|
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|
|
2-Tone IMD = ±82.4 dBFS |
|
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|
|
THD = 73.3 dBc |
|
−40 |
|
|
SFDR = ±87.8 dBFS |
|
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− dB |
−60 |
|
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Amplitude |
−80 |
|
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−100 |
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−120 |
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−140 |
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−160 |
|
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0 |
10 |
20 |
30 |
40 |
50 |
0 |
10 |
20 |
30 |
40 |
50 |
|
|
f − Frequency − MHz |
G021 |
|
|
f − Frequency − MHz |
|
G022 |
|||
|
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|
|
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|
||
Figure 29. |
Figure 30. |
SFDR vs INPUT FREQUENCY |
SNR vs INPUT FREQUENCY |
|
96 |
|
|
|
|
|
|
|
|
|
|
76 |
|
92 |
|
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|
74 |
|
|
|
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|
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|
88 |
|
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72 |
|
84 |
|
|
|
|
Gain = 3.5 dB |
|
|
|
|||
− dBc |
|
|
|
|
|
|
dBFS |
|
||||
80 |
|
|
|
|
|
|
|
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|
70 |
||
SFDR |
76 |
|
|
|
Gain = 0 dB |
|
|
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|
SNR − |
68 |
|
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||||
72 |
|
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||
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66 |
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68 |
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64 |
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64 |
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60 |
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62 |
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0 |
50 |
100 |
150 |
200 |
250 |
300 |
350 |
400 |
450 |
500 |
|
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|
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fIN − Input Frequency − MHz |
|
|
G023 |
|
||||
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Gain = 0 dB |
|
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||
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Gain = 3.5 dB |
|
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||
0 |
50 |
100 |
150 |
200 |
250 |
300 |
350 |
400 |
450 |
500 |
|
|
|
fIN − Input Frequency − MHz |
|
|
G024 |
||||
|
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|
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|
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|
|
Figure 31. |
Figure 32. |
28 |
Submit Documentation Feedback |
Copyright © 2007–2008, Texas Instruments Incorporated |
Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122
ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER 2007–REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6124 (FS= 105 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted)
SFDR vs INPUT FREQUENCY (LVDS interface) |
SNR vs INPUT FREQUENCY (LVDS interface) |
|
96 |
|
|
|
|
|
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|
76 |
|
92 |
|
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|
74 |
|
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|
88 |
|
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72 |
|
84 |
|
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− dBc |
|
|
|
|
Gain = 3.5 dB |
|
|
dBFS |
|
|||
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|
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|
70 |
|||||
80 |
|
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|
|
|
|
|
|
|
|||
SFDR |
76 |
|
|
Gain = 0 dB |
|
|
|
|
SNR − |
68 |
||
72 |
|
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|||||
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66 |
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68 |
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64 |
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64 |
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60 |
|
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|
62 |
|
0 |
50 |
100 |
150 |
200 |
250 |
300 |
350 |
400 |
450 |
500 |
|
|
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|
|
fIN − Input Frequency − MHz |
|
|
G025 |
|
||||
|
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|
|
Gain = 0 dB |
|
|
|
||
|
Gain = 3.5 dB |
|
|
|
|
|
|
|
||
0 |
50 |
100 |
150 |
200 |
250 |
300 |
350 |
400 |
450 |
500 |
|
|
|
fIN − Input Frequency − MHz |
|
|
G026 |
||||
|
|
|
|
|
|
|
|
|
|
|
Figure 33. |
Figure 34. |
SFDR vs INPUT FREQUENCY ACROSS GAINS |
SINAD vs INPUT FREQUENCY ACROSS GAINS |
|
95 |
|
|
|
|
|
|
76 |
|
|
|
Input adjusted to get −1dBFS input |
|
74 |
|||
|
90 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
85 |
|
|
6 dB |
5 dB |
|
|
72 |
|
|
|
|
|
|
dBFS |
|
|
dBc |
80 |
|
|
|
|
|
70 |
|
|
|
|
|
|
|
|||
− |
|
|
|
|
|
|
− |
68 |
SFDR |
|
0 dB |
|
|
|
|
SINAD |
|
75 |
1 dB |
|
|
4 dB |
|
|||
|
|
|
66 |
|||||
|
|
|
|
|
|
|||
|
|
|
|
|
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|
||
|
70 |
|
|
2 dB |
|
|
|
64 |
|
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||
|
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|
|
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|
65 |
|
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|
62 |
|
|
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|
3 dB |
|
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|
60 |
|
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|
|
60 |
|
0 |
100 |
200 |
300 |
400 |
|
500 |
|
|
|
|
fIN − Input Frequency − MHz |
|
G027 |
|
||
|
|
|
|
|
|
|
|
|
|
|
Input adjusted to get −1dBFS input |
|
||
|
0 dB |
1 dB |
|
|
|
|
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|
|
|
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|
|
2 dB |
|
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|
3 dB |
4 dB |
|
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|
5 dB |
6 dB |
|
|
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|
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0 |
100 |
200 |
300 |
400 |
500 |
|
|
fIN − Input Frequency − MHz |
|
G028 |
|
|
|
|
|
|
|
Figure 35. |
Figure 36. |
PERFORMANCE vs AVDD |
PERFORMANCE vs DRVDD |
|
92 |
|
|
|
|
|
78 |
|
|
98 |
|
|
|
|
|
|
|
|
|
77 |
|
|
90 |
fIN = 70.1 MHz |
|
|
|
|
77 |
|
|
96 |
|
fIN = 10.1 MHz |
|
|
|
|
|
|
76 |
|
|
|
DRVDD = 3.3 V |
|
|
|
|
|
|
|
AVDD = 3.3 V |
|
|
|
|
|
|
|
|||||
|
88 |
|
|
|
|
|
76 |
|
|
94 |
|
|
|
|
|
|
|
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|
75 |
|
|
|
|
|
|
|
|
|
|
|
|
SFDR |
|
|
|
|
|
|
|
|
||
− dBc |
86 |
|
|
|
|
|
75 |
dBFS |
− dBc |
|
|
|
|
|
|
|
|
|
|
dBFS |
|
|
|
SFDR |
|
|
92 |
|
|
|
|
|
|
|
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|
74 |
||||||
|
|
|
|
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|
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|
|||||||
84 |
|
|
|
|
|
74 |
|
|
|
|
|
|
|
|
|
|
|
||||
SFDR |
|
|
|
|
|
SNR − |
SFDR |
|
|
|
|
|
|
|
|
|
|
|
SNR − |
||
82 |
|
|
|
|
|
73 |
90 |
|
|
|
|
|
|
|
|
|
73 |
||||
|
|
|
|
|
|
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|
|
|
|
SNR |
|
|
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|
||||||
|
|
|
|
|
|
|
|
|
|
88 |
|
|
|
|
|
|
|
|
72 |
|
|
|
80 |
|
|
SNR |
|
|
72 |
|
|
|
|
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|
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||
|
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|||
|
78 |
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71 |
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86 |
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71 |
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||
|
76 |
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|
70 |
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|
84 |
|
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|
70 |
|
|
3.0 |
3.1 |
3.2 |
3.3 |
3.4 |
3.5 |
3.6 |
|
|
|
1.8 |
2.0 |
2.2 |
2.4 |
2.6 |
2.8 |
3.0 |
3.2 |
3.4 |
3.6 |
|
|
|
AVDD − Supply V oltage − V |
|
|
G029 |
|
|
|
|
DRVDD − Supply V oltage − V |
|
|
|
G030 |
|||||||
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||
|
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|
|
Figure 37. |
|
|
|
|
|
|
|
|
|
|
Figure 38. |
|
|
|
|
||
Copyright © 2007–2008, Texas Instruments Incorporated |
Submit Documentation Feedback |
29 |
Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122
ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER 2007–REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6124 (FS= 105 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted)
PERFORMANCE vs TEMPERATURE |
PERFORMANCE vs INPUT AMPLITUDE |
|
96 |
|
|
|
|
|
|
|
|
|
SFDR |
|
|
|
|
|
94 |
|
|
|
|
|
|
− dBc |
92 |
|
|
|
|
|
|
|
|
|
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|
|
|
|
SFDR |
90 |
|
SNR |
|
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|
|
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||
|
|
|
|
|
|
|
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|
88 |
|
|
|
|
|
|
|
|
fIN = 10.1 MHz |
|
|
|
|
|
|
86 |
|
|
|
|
|
|
|
−40 |
−20 |
0 |
20 |
40 |
60 |
80 |
|
|
|
|
T − T emperature − °C |
|
|
|
75 |
|
|
110 |
|
|
|
|
|
90 |
|
|
|
|
100 |
|
SFDR (dBFS) |
|
|
85 |
|
|
74 |
|
|
90 |
|
|
|
|
|
80 |
|
|
|
dBc, dBFS |
|
|
|
|
|
|
||
73 |
− dBFS |
80 |
|
SNR (dBFS) |
|
|
75 |
− dBFS |
||
|
|
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|
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|
||||
|
70 |
|
|
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|
70 |
|||
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|
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|
|
|
|||
72 |
SNR |
SFDR − |
60 |
|
|
|
|
|
65 |
SNR |
|
SFDR (dBc) |
|
|
|
|
|||||
|
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||||
|
50 |
|
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60 |
|||
71 |
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|
|
|
|
|
40 |
|
|
|
|
|
55 |
|
|
|
|
|
|
|
|
|
fIN = 20.1 MHz |
|
|
70 |
|
|
30 |
|
|
|
|
|
50 |
|
|
|
|
−60 |
−50 |
−40 |
−30 |
−20 |
−10 |
0 |
|
|
G031 |
|
|
|
Input Amplitude − dBFS |
|
|
G032 |
||
|
|
|
|
|
|
|
|
|
||
Figure 39. |
Figure 40. |
PERFORMANCE vs CLOCK AMPLITUDE |
PERFORMANCE vs INPUT CLOCK DUTY CYCLE |
|
92 |
|
SNR |
|
|
72.0 |
|
|
96 |
|
|
|
|
|
|
|
|
|
|
|
90 |
|
|
|
|
71.5 |
|
|
94 |
|
88 |
|
|
|
|
71.0 |
|
|
92 |
− dBc |
86 |
|
SFDR |
|
|
70.5 |
dBFS |
− dBc |
90 |
|
|
|
|
||||||
84 |
|
|
|
|
70.0 |
88 |
|||
SFDR |
|
|
|
|
SNR − |
SFDR |
|||
82 |
|
|
|
|
69.5 |
86 |
|||
|
80 |
|
|
|
|
69.0 |
|
|
84 |
|
78 |
fIN = 20.1 MHz |
|
|
68.5 |
|
|
82 |
|
|
76 |
|
|
68.0 |
|
|
80 |
||
|
|
|
|
|
|
|
|||
|
0.5 |
1.0 |
1.5 |
2.0 |
2.5 |
3.0 |
|
|
|
|
|
|
Input Clock Amplitude − V PP |
|
|
G033 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
72.0 |
|
|
fIN = 10.1 MHz |
SFDR |
|
|
|
71.5 |
|
||
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
71.0 |
|
|
|
|
|
|
SNR |
|
|
70.5 |
− dBFS |
|
|
|
|
|
|
|
|
70.0 |
|
|
|
|
|
|
|
|
|
69.5 |
SNR |
|
|
|
|
|
|
|
|
69.0 |
|
|
|
|
|
|
|
|
|
68.5 |
|
|
|
|
|
|
|
|
|
68.0 |
|
30 |
35 |
40 |
45 |
50 |
55 |
60 |
65 |
70 |
|
|
|
|
Input Clock Duty Cycle − % |
|
|
|
G034 |
||
|
|
|
|
|
|
|
|
|
|
Figure 41. |
Figure 42. |
PERFORMANCE IN EXTERNAL REFERENCE MODE
|
96 |
fIN = 20.1 MHz |
|
|
|
|
76 |
|
||
|
|
|
|
|
|
|
|
|||
|
|
External Reference Mode |
|
|
|
|
|
|||
|
94 |
|
|
|
|
|
|
|
74 |
|
− dBc |
92 |
|
|
SNR |
|
|
|
|
72 |
dBFS |
|
|
|
|
|
|
|
|
|
||
SFDR |
90 |
|
|
|
|
|
|
|
70 |
SNR − |
|
|
|
|
|
|
|
|
|
||
|
|
|
|
SFDR |
|
|
|
|
|
|
|
88 |
|
|
|
|
|
|
|
68 |
|
|
86 |
|
|
|
|
|
|
|
66 |
|
|
1.30 |
1.35 |
1.40 |
1.45 |
1.50 |
1.55 |
1.60 |
1.65 |
1.70 |
|
|
|
|
|
VVCM − VCM V oltage − V |
|
|
|
G036 |
||
|
|
|
|
|
|
|
|
|
|
|
Figure 43.
30 |
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Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122
