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ADS6125, ADS6124

ADS6123, ADS6122

www.ti.com

SLAS560A–OCTOBER 2007–REVISED MARCH 2008

TIMING CHARACTERISTICS – LVDS AND CMOS MODES(1)

Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF(2), IO = 3.5

mA, RL = 100 Ω (3), no internal termination, unless otherwise noted.

For timings at lower sampling frequencies, see section Output Timings in the APPLICATION INFORMATION of this data sheet.

	PARAMETER	TEST CONDITIONS
ta	Aperture
ta	delay
	delay
tj	Aperture
tj	jitter
	jitter
		From global power
	Wake-up	down
	Wake-up
	time	From standby
	(to valid	From output	CMOS
	data)	From output	CMOS
	data)	buffer
		buffer	LVDS
		disable	LVDS

Latency

DDR LVDS MODE(4), DRVDD = 3.3 V

tsu	Data setup
tsu	time(5)
th	Data hold
th	time(5)
	Clock
tPDI	propagation
	delay
	LVDS bit
	clock duty
	cycle

Data valid (6) to zero-cross of CLKOUTP

Zero-cross of CLKOUTP to data becoming invalid(6)

Input clock rising edge zero-cross to output clock rising edge zero-cross

Duty cycle of differential clock, (CLKOUTPCLKOUTM)

10 ≤ Fs ≤ 125 MSPS

	ADS6125			ADS6124			ADS6123			ADS6122
FS = 125 MSPS			FS = 105 MSPS			FS = 80 MSPS			FS = 65 MSPS			UNIT
MIN	TYP	MAX	MIN	TYP	MAX	MIN	TYP	MAX	MIN	TYP	MAX
0.7	1.5	2.5	0.7	1.5	2.5	0.7	1.5	2.5	0.7	1.5	2.5	ns
	150			150			150			150		fs rms
	15	50		15	50		15	50		15	50	μs
	15	50		15	50		15	50		15	50	μs
	100	200		100	200		100	200		100	200	ns
	200	500		200	500		200	500		200	500	ns
	9			9			9			9		clock
	9			9			9			9		cycles
												cycles
1.7	2.3		2.5	3.1		3.9	4.5		5.4	6.0		ns
0.7	1.7		0.7	1.7		0.7	1.7		0.7	1.7		ns
4.3	5.8	7.3	4.3	5.8	7.3	4.3	5.8	7.3	4.3	5.8	7.3	ns
40%	47%	55%	40%	47%	55%	40%	47%	55%	40%	47%	55%

	Data rise
tr	time,
tf	Data fall
	time
tCLKRI	Output clock
SE	rise time,
tCLKFA	Output clock
LL	fall time

Rise time measured
from –50 mV to 50 mV
Fall time measured	70	100	170	70	100	170
from 50 mV to –50 mV
1 ≤ Fs ≤ 125 MSPS
Rise time measured
from –50 mV to 50 mV
Fall time measured	70	100	170	70	100	170
from 50 mV to –50 mV
1 ≤ Fs ≤ 125 MSPS

PARALLEL CMOS MODE, DRVDD = 2.5 V to 3.3 V, default output buffer drive strength (7)

tsu	Data setup		Data valid(8) to 50% of	2.9	4.4		3.6	5.1
tsu	time(5)		CLKOUT rising edge	2.9	4.4		3.6	5.1
	Data hold		50% of CLKOUT
th	Data hold		Rising edge to data	1.3	2.7		2.1	3.5
th	time	(5)	Rising edge to data	1.3	2.7		2.1	3.5
	time		becoming invalid(8)
	Clock		Input clock rising edge
tPDI	propagation		zero-cross to 50% of	5	6.5	7.9	5	6.5	7.9
	delay		CLKOUT rising edge

70	100	170	70	100	170	ps
70	100	170	70	100	170	ps
5.1	6.6		6.5	8.0		ns
3.6	5.0		5.1	6.5		ns
5	6.5	7.9	5	6.5	7.9	ns

(1)Timing parameters are specified by design and characterization and not tested in production.

(2)CL is the Effective external single-ended load capacitance between each output pin and ground.

(3)IO Refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair.

(4)Measurements are done with a transmission line of 100 Ω characteristic impedance between the device and the load.

(5)Setup and hold time specifications take into account the effect of jitter on the output data and clock.

(6)Data valid refers to logic high of +100 mV and logic low of –100 mV.

(7)For DRVDD < 2.2V, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT). See

Parallel CMOS interface in application section.

(8)Data valid refers to logic high of 2V (1.7V) and logic low of 0.8 V (0.7V) for DRVDD = 3.3V (2.5V).

Submit Documentation Feedback

Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

ADS6125, ADS6124

ADS6123, ADS6122

www.ti.com

SLAS560A–OCTOBER 2007–REVISED MARCH 2008

TIMING CHARACTERISTICS – LVDS AND CMOS MODES (continued)

For timings at lower sampling frequencies, see section Output Timings in the APPLICATION INFORMATION of this data sheet.

PARAMETER
	Output clock
	duty cycle
	Data rise
tr	time,
tf	Data fall
	time
tCLKRI	Output clock
SE	rise time,
tCLKFA	Output clock
LL	fall time

		ADS6125			ADS6124			ADS6123			ADS6122
TEST CONDITIONS	FS = 125 MSPS			FS = 105 MSPS			FS = 80 MSPS			FS = 65 MSPS			UNIT
	MIN	TYP	MAX	MIN	TYP	MAX	MIN	TYP	MAX	MIN	TYP	MAX
Duty cycle of output
clock (CLKOUT)	45%	50%	55%	45%	50%	55%	45%	50%	55%	45%	50%	55%
10 ≤ Fs ≤ 125 MSPS
Rise time measured
from 20% to 80% of
DRVDD
Fall time measured	0.8	1.5	2.4	0.8	1.5	2.4	0.8	1.5	2.4	0.8	1.5	2.4	ns
from 80% to 20% of
DRVDD
1 ≤ Fs ≤ 125 MSPS
Rise time measured
from 20% to 80% of
DRVDD
Fall time measured	0.8	1.5	2.4	0.8	1.5	2.4	0.8	1.5	2.4	0.8	1.5	2.4	ns
from 80% to 20% of
DRVDD
1 ≤ Fs ≤ 125 MSPS

Submit Documentation Feedback

Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

		ADS6125, ADS6124
www.ti.com		ADS6123, ADS6122
		SLAS560A–OCTOBER 2007–REVISED MARCH 2008
N+3	N+4	N+11	N+12
N+2		N+10
N+2
Sample N+1		N+9
N

Input

Signal

CLKP

Input

Clock

CLKM

CLKOUTM

CLKOUTP

tsu

tPDI

DDR

9 Clock Cycles

LVDS

Output Data

O E

O E O E O E

O E

O E O E

DXP, DXM

E – Even Bits D0,D2,D4,D6,D8,D10

N–9

N–8

N–7

N–6

N–5

N–1

N+1

N+2

O – Odd Bits D1,D3,D5,D7,D9,D11

tPDI

CLKOUT
Parallel								tsu
Parallel			9 Clock Cycles						th
CMOS			9 Clock Cycles
CMOS
Output Data	N–9	N–8	N–7	N–6	N–5	N–1	N	N+1	N+2
D0–D11	N–9	N–8	N–7	N–6	N–5	N–1	N	N+1	N+2
D0–D11

Figure 1. Latency

Input

CLKM

Clock

CLKP

Input

Clock

CLKP

Output

CLKOUTM

tPDI

Clock

CLKOUTP

Output

CLKOUT

Clock

tsu

Output

Dn_Dn+1_P,

Dn(1)

Dn+1(2)

Data Pair

Dn_Dn+1_M

Output

Dn(1)

Data

(1)Dn – Bits D0, D2, D4, D6, D8, D10
(2)Dn+1 – Bits D1, D3, D5, D7, D9, D11	(1)Dn – Bits D0–D11
Figure 2. LVDS Mode Timing	Figure 3. CMOS Mode Timing

Submit Documentation Feedback

Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122

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70	100	170	70	100	170	ps
70	100	170	70	100	170	ps
5.1	6.6		6.5	8.0		ns
3.6	5.0		5.1	6.5		ns
5	6.5	7.9	5	6.5	7.9	ns

70	100	170	70	100	170	ps
70	100	170	70	100	170	ps
5.1	6.6		6.5	8.0		ns
3.6	5.0		5.1	6.5		ns
5	6.5	7.9	5	6.5	7.9	ns

70	100	170	70	100	170	ps
70	100	170	70	100	170	ps
5.1	6.6		6.5	8.0		ns
3.6	5.0		5.1	6.5		ns
5	6.5	7.9	5	6.5	7.9	ns