- •FEATURES
- •APPLICATIONS
- •DESCRIPTION
- •ABSOLUTE MAXIMUM RATINGS
- •RECOMMENDED OPERATING CONDITIONS
- •ELECTRICAL CHARACTERISTICS
- •ELECTRICAL CHARACTERISTICS
- •DIGITAL CHARACTERISTICS
- •TIMING CHARACTERISTICS – LVDS AND CMOS MODES
- •DEVICE PROGRAMMING MODES
- •USING SERIAL INTERFACE PROGRAMMING ONLY
- •USING PARALLEL INTERFACE CONTROL ONLY
- •SERIAL INTERFACE
- •REGISTER INITIALIZATION
- •SERIAL INTERFACE TIMING
- •RESET TIMING
- •SERIAL REGISTER MAP
- •DESCRIPTION OF SERIAL REGISTERS
- •TYPICAL CHARACTERISTICS - ADS6125 (FS= 125 MSPS)
- •TYPICAL CHARACTERISTICS - ADS6124 (FS= 105 MSPS)
- •TYPICAL CHARACTERISTICS - ADS6123 (FS= 80 MSPS)
- •TYPICAL CHARACTERISTICS - ADS6122 (FS= 65 MSPS)
- •TYPICAL CHARACTERISTICS - LOW SAMPLING FREQUENCIES
- •FS = 40 MSPS
- •FS = 25 MSPS
- •COMMON PLOTS
- •Contour Plots Across Input and Sampling Frequencies
- •APPLICATION INFORMATION
- •THEORY OF OPERATION
- •ANALOG INPUT
- •Drive Circuit Requirements
- •Using RF-Transformer Based Drive Circuits
- •Using Differential Amplifier Drive Circuits
- •Input Common-Mode
- •REFERENCE
- •Internal Reference
- •External Reference
- •COARSE GAIN and PROGRAMMABLE FINE GAIN
- •CLOCK INPUT
- •POWER DOWN MODES
- •Global Powerdown
- •Standby
- •Output Buffer Disable
- •Input Clock Stop
- •Power Supply Sequence
- •DIGITAL OUTPUT INTERFACE
- •Parallel CMOS Interface
- •DDR LVDS Interface
- •Output Data Format
- •Output Timings
- •BOARD DESIGN CONSIDERATIONS
- •Grounding
- •Supply Decoupling
- •Exposed Thermal Pad
- •DEFINITION OF SPECIFICATIONS
- •Analog Bandwidth
- •Aperture Delay
- •Aperture Uncertainty (Jitter)
- •Clock Pulse Width/Duty Cycle
- •Maximum Conversion Rate
- •Minimum Conversion Rate
- •Differential Nonlinearity (DNL)
- •Integral Nonlinearity (INL)
- •Gain Error
- •Offset Error
- •Temperature Drift
- •Signal-to-Noise Ratio
- •Signal-to-Noise and Distortion (SINAD)
- •Effective Number of Bits (ENOB)
- •Total Harmonic Distortion (THD)
- •Spurious-Free Dynamic Range (SFDR)
- •Two-Tone Intermodulation Distortion
- •DC Power Supply Rejection Ratio (DC PSRR)
- •AC Power Supply Rejection Ratio (AC PSRR)
- •Common Mode Rejection Ratio (CMRR)
- •Voltage Overload Recovery
ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER 2007–REVISED MARCH 2008
BOARD DESIGN CONSIDERATIONS
Grounding
A single ground plane is sufficient to give good performance, provided the analog, digital and clock sections of the board are cleanly partitioned. See the EVM User Guide (SLWU028) for details on layout and grounding.
Supply Decoupling
As ADS612X already includes internal decoupling, minimal external decoupling can be used without loss in performance. Note that decoupling capacitors can help to filter external power supply noise, so the optimum number of capacitors would depend on the actual application. The decoupling capacitors should be placed very close to the converter supply pins.
It is recommended to use separate supplies for the analog and digital supply pins to isolate digital switching noise from sensitive analog circuitry. In case only a single 3.3-V supply is available, it should be routed first to AVDD. It can then be tapped and isolated with a ferrite bead (or inductor) with decoupling capacitor, before being routed to DRVDD.
Exposed Thermal Pad
It is necessary to solder the exposed pad at the bottom of the package to a ground plane for best thermal performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and QFN/SON PCB Attachment (SLUA271).
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Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122
