ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER 2007–REVISED MARCH 2008
Figure 104. LVDS Eye Diagram - No Internal Termination |
Figure 105. LVDS Eye Diagram with 100-Ω Internal |
5-pF Load Capacitance |
Termination |
Blue Trace - Output Clock (CLKOUT) |
10-pF Load Capacitance |
Pink Trace - Output Data |
Blue Trace - Output Clock (CLKOUT) |
|
Pink Trace - Output Data |
Output Data Format
Two output data formats are supported – 2s complement and offset binary. They can be selected using the parallel control pin SEN or the serial interface register bit <DATA FORMAT> (see Table 8).
Output Timings
The following table lists the timings at lower sampling frequencies.
Table 17. Timing Characteristics at Lower Sampling Frequencies (1)(2)
Fs, MSPS |
tsu DATA SETUP TIME, ns |
|
th DATA HOLD TIME, ns |
|
tPDI CLOCK PROPAGATION DELAY, ns |
|||||
MIN |
TYP |
MAX |
MIN |
TYP |
MAX |
MIN |
TYP |
MAX |
||
|
||||||||||
CMOS INTERFACE, DRVDD = 2.5 V to 3.3 V |
|
|
|
|
|
|
|
|||
40 |
11.3 |
12.8 |
|
10 |
11.2 |
|
5 |
6.5 |
7.9 |
|
20 |
23 |
25 |
|
21 |
23 |
|
|
|
|
|
10 |
48 |
50 |
|
46 |
48 |
|
|
|
|
|
DDR LVDS INTERFACE, DRVDD = 3.3 V |
|
|
|
|
|
|
|
|||
40 |
10.2 |
10.8 |
|
0.7 |
1.7 |
|
4.3 |
5.8 |
7.3 |
|
20 |
22 |
23 |
|
0.7 |
1.7 |
|
4.5 |
6.5 |
8.5 |
|
10 |
47 |
48 |
|
0.7 |
1.7 |
|
4.5 |
6.5 |
8.5 |
|
(1)Timing parameters are specified by design and characterization and not tested in production.
(2)Timings are specified with default output buffer drive strength and CL= 5 pF
54 |
Submit Documentation Feedback |
Copyright © 2007–2008, Texas Instruments Incorporated |
Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122